MC74HCT244A
Octal 3−State NoninvertingBuffer/Line Driver/Line Receiver with
LSTTL−Compatible Inputs
High−Performance Silicon−Gate CMOS
The MC74HCT244A is identical in pinout to the LS244. Thisdevice may be used as a level converter for interfacing TTL or NMOSoutputs to High−Speed CMOS inputs. The HCT244A is an octalnoninverting buffer line driver line receiver designed to be used with3−state memory address drivers, clock drivers, and other bus−orientedsystems. The device has non−inverted outputs and two active−lowoutput enables.
The HCT244A is the non−inverting version of the HCT240. Seealso HCT241.
Features
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PDIP−20N SUFFIXCASE 738
1SOIC−20WDW SUFFIXCASE 751D
1••••••••
Output Drive Capability: 15 LSTTL LoadsTTL NMOS−Compatible Input Levels
Outputs Directly Interface to CMOS, NMOS, and TTLOperating Voltage Range: 4.5 to 5.5 VLow Input Current: 1 mA
In Compliance with the Requirements Defined by JEDEC StandardNo. 7A
Chip Complexity: 112 FETs or 28 Equivalent GatesPb−Free Packages are Available
TSSOP−20DT SUFFIXCASE 948E
1SOEIAJ−20M SUFFIXCASE 967
1
PIN ASSIGNMENTENABLE AA1YB4A21234567891020191817161514131211VCCENABLE BYA1B4YA2B3YA3B2YA4B1A1A2A3A4B1B2B3B4
246811131517181614129753YA1YA2YA3YA4YB1YB2YB3YB4NONINVERTINGOUTPUTS
YB3A3YB2A4YB1GNDDATA INPUTSFUNCTION TABLEInputsEnable A,Enable BLLHA, BLHXOutputsYA, YBLHZ1OUTPUTENABLE AENABLESENABLE B19PIN 20 = VCCPIN 10 = GNDZ = high impedance, X = don’t careFigure 1. Logic DiagramORDERING AND MARKING INFORMATION
See detailed ordering, shipping, and marking information inthe package dimensions section on page 5 of this data sheet.
© Semiconductor Components Industries, LLC, 20061December, 2006 − Rev. 11
Publication Order Number:
MC74HCT244A/D
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MC74HCT244A
MAXIMUM RATINGS
SymbolVCCVin
ParameterValueUnitVVVmAmAmAmW
DC Supply Voltage (Referenced to GND)DC Input Voltage (Referenced to GND)DC Output Voltage (Referenced to GND)DC Input Current, per PinDC Output Current, per Pin
DC Supply Current, VCC and GND PinsPower Dissipation in Still Air,
– 0.5 to + 7– 0.5 to VCC + 0.5– 0.5 to VCC + 0.5
±20±35
VoutIin
Iout
ICCPD
± 75750
500450
Plastic DIP†
SOIC Package†TSSOP Package†
TstgTL
Storage Temperature– 65 to + 150
260
_C_C
This device contains protection
circuitry to guard against damagedue to high static voltages or electricfields. However, precautions mustbe taken to avoid applications of anyvoltage higher than maximum ratedvoltages to this high−impedance cir-cuit. For proper operation, Vin andVout should be constrained to therange GND v (Vin or Vout) v VCC.Unused inputs must always betied to an appropriate logic voltagelevel (e.g., either GND or VCC).Unused outputs must be left open.
Lead Temperature, 1 mm from Case for 10 Seconds
(Plastic DIP, SOIC, SSOP or TSSOP Package)
†Derating−Plastic DIP: – 10 mW/_C from 65_ to 125_C
−SOIC Package: – 7 mW/_C from 65_ to 125_C −TSSOP Package: − 6.1 mW/_C from 65_ to 125_C
For high frequency or heavy load considerations, see Chapter 2 of the ON Semiconductor High−Speed CMOS Data Book (DL129/D).
RECOMMENDED OPERATING CONDITIONS
SymbolVCCVin, Vout
TAtr, tf
Parameter
DC Supply Voltage (Referenced to GND)
DC Input Voltage, Output Voltage (Referenced to GND)Operating Temperature, All Package TypesInput Rise and Fall Time (Figure 1)
Min4.50– 550
Max5.5VCC+ 125500
UnitVV_Cns
DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND)
Guaranteed Limit
v 85_C
2
2
SymbolVIHVIL
ParameterTest Conditions
VCC
V4.55.54.55.54.55.54.54.55.54.55.55.55.5
– 55 to25_C22
v 125_C
22
UnitVVV
Minimum High−Level Input VoltageMaximum Low−Level InputVoltage
Vout = 0.1 V or VCC – 0.1 V
|Iout| v 20 mA
Vout = 0.1 V or VCC – 0.1 V|Iout| v 20 mAVin = VIH or VIL|Iout| v 20 mAVin = VIH or VIL|Iout| v 6 mAVin = VIH or VIL|Iout| v 20 mAVin = VIH or VIL|Iout| v 6 mA
0.8
0.84.45.4
0.80.84.45.4
0.80.84.45.43.70.10.10.4
VOH
Minimum High−Level Output
Voltage
3.980.1
0.1
3.840.10.1
VOL
Maximum Low−Level Output
Voltage
V
0.26±0.1±0.54
0.33±1.0±5.040
IinIOZICC
Maximum Input Leakage CurrentMaximum Three−State Leakage
Current
Maximum Quiescent SupplyCurrent (per Package)
Vin = VCC or GND
Output in High−Impedance StateVin = VIL or VIH; Vout = VCC or GNDVin = VCC or GND Iout = 0 mA
±1.0±10160
mAmAmA
DICC
Additional Quiescent Supply
Current
Vin = 2.4 V, Any One Input
Vin = VCC or GND, Other Inputslout = 0 mA
≥ −55_C2.9
25_C to 125_C
2.4
5.5mA
1.Information on typical parametric values along with frequency or heavy load considerations can be found in Chapter 2 of the ONSemiconductor High−Speed CMOS Data Book (DL129/D).2.Total Supply Current = ICC + ΣDICC.
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MC74HCT244A
AC ELECTRICAL CHARACTERISTICS (VCC = 5.0 V ± 10%, CL = 50 pF, Input tr = tf = 6 ns)
Guaranteed Limit
v 85_C253328151015
SymboltPLH,
tPHLtPLZ,tPHZtPZL,tPZH
Parameter
– 55 to 25_C
202622121015
v 125_C
303933181015
UnitnsnsnsnspFpF
Maximum Propagation Delay, A to YA or B to YB
(Figures 1 and 3)
Maximum Propagation Delay, Output Enable to YA or YB
(Figures 2 and 4)Maximum Propagation Delay, Output Enable to YA or YB(Figures 2 and 4)Maximum Output Transition Time, Any Output(Figures 1 and 3)Maximum Input Capacitance
tTLH,
tTHLCin
Cout
Maximum Three−State Output Capacitance
(Output in High−Impedance State)
NOTE:For propagation delays with loads other than 50 pF, and information on typical parametric values, see Chapter 2 of the ON
Semiconductor High−Speed CMOS Data Book (DL129/D).
Typical @ 25°C, VCC = 5.0 V
CPD
Power Dissipation Capacitance (Per Enabled Output)*
55
pF
*Used to determine the no−load dynamic power consumption: PD = CPD VCC2f + ICC VCC. For load considerations, see Chapter 2 of theON Semiconductor High−Speed CMOS Data Book (DL129/D).
SWITCHING WAVEFORMS
tr2.7 V1.3 V0.3 VtPLH90%1.3 V10%tTLHtPHLtfINPUTA OR BOUTPUTYA OR YB3 VGND
tTHLFigure 2. 3 VENABLEA OR B
1.3 VtPZL1.3 VtPZHOUTPUT Y
1.3 VtPHZtPLZ10%90%GNDHIGHIMPEDANCEVOLVOHHIGHIMPEDANCEOUTPUT Y
Figure 3.
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MC74HCT244A
TEST CIRCUITS
TEST POINTOUTPUTDEVICEUNDERTESTCL*
*Includes all probe and jig capacitance
Figure 4.
TEST POINTOUTPUTDEVICEUNDERTEST1 kWCONNECT TO VCC WHENTESTING tPLZ AND tPZL.CONNECT TO GND WHENTESTING tPHZ AND tPZH.
CL**Includes all probe and jig capacitance
Figure 5.
LOGIC DETAIL
TO THREE OTHERA OR B INVERTERS
ONE OF 8BUFFERSVCCDATA INPUT
A OR B
YAORYB
ENABLE A OR ENABLE B
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MC74HCT244A
ORDERING INFORMATION
Device
MC74HCT244ANMC74HCT244ANGMC74HCT244ADWMC74HCT244ADWGMC74HCT244ADWR2MC74HCT244ADWR2GMC74HCT244ADTR2MC74HCT244ADTR2GMC74HCT244AFMC74HCT244AFGMC74HCT244AFELMC74HCT244AFELG
PackagePDIP−20PDIP−20(Pb−Free)SOIC−20SOIC−20(Pb−Free)SOIC−20SOIC−20(Pb−Free)TSSOP−20*TSSOP−20*SOEIAJ−20SOEIAJ−20(Pb−Free)SOEIAJ−20SOEIAJ−20(Pb−Free)
2000 / Tape & Reel40 Units / Rail1000 / Tape & Reel38 Units / Rail18 Units / RailShipping†
2500 / Tape & Reel
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel PackagingSpecifications Brochure, BRD8011/D.*These packages are inherently Pb−Free.
MARKING DIAGRAMS
PDIP−20SOIC−20WTSSOP−20SOEIAJ−20
2020
MC74HCT244ANAWLYYWWG
1
1HCT244AAWLYYWWG20
HCT244AALYWGG1
20
74HCT244AAWLYWWG
1
A= Assembly LocationWL, L= Wafer LotYY, Y= Year
WW, W= Work Week
G or G= Pb−Free Package
(Note: Microdot may be in either location)
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MC74HCT244A
PACKAGE DIMENSIONS
PDIP−20N SUFFIX
PLASTIC DIP PACKAGE
CASE 738−03ISSUE E
−A−20111NOTES:
1.DIMENSIONING AND TOLERANCING PER ANSIY14.5M, 1982.
2.CONTROLLING DIMENSION: INCH.
3.DIMENSION L TO CENTER OF LEAD WHENFORMED PARALLEL.
4.DIMENSION B DOES NOT INCLUDE MOLDFLASH.
B10CL−T−SEATINGPLANEKMEGFD20 PLNJ0.25 (0.010)M20 PL0.25 (0.010)TAMMTBMDIMABCDEFGJKLMNINCHESMINMAX1.0101.0700.2400.2600.1500.1800.0150.0220.050 BSC0.0500.0700.100 BSC0.0080.0150.1100.1400.300 BSC0 _15 _0.0200.040MILLIMETERSMINMAX25.6627.176.106.603.814.570.390.551.27 BSC1.271.772.54 BSC0.210.382.803.557.62 BSC0 _15 _0.511.01SOIC−20W
DW SUFFIXCASE 751D−05
ISSUE G
DA11X 45_qHMBM2010X0.25ENOTES:1.DIMENSIONS ARE IN MILLIMETERS.2.INTERPRET DIMENSIONS AND TOLERANCESPER ASME Y14.5M, 1994.3.DIMENSIONS D AND E DO NOT INCLUDE MOLDPROTRUSION.4.MAXIMUM MOLD PROTRUSION 0.15 PER SIDE.5.DIMENSION B DOES NOT INCLUDE DAMBARPROTRUSION. ALLOWABLE PROTRUSIONSHALL BE 0.13 TOTAL IN EXCESS OF BDIMENSION AT MAXIMUM MATERIALCONDITION.DIMAA1BCDEeHhLqMILLIMETERSMINMAX2.352.650.100.250.350.490.230.3212.6512.957.407.601.27 BSC10.0510.550.250.750.500.900 7 __11020XB0.25MBTASBSAeSEATINGPLANEh18XA1TChttp://onsemi.com
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MC74HCT244A
PACKAGE DIMENSIONS
TSSOP−20DT SUFFIXCASE 948E−02
ISSUE C
20X REFKNOTES:1.DIMENSIONING AND TOLERANCING PERANSI Y14.5M, 1982.
2.CONTROLLING DIMENSION:MILLIMETER.
3.DIMENSION A DOES NOT INCLUDEMOLD FLASH, PROTRUSIONS OR GATEBURRS. MOLD FLASH OR GATE BURRSSHALL NOT EXCEED 0.15 (0.006) PER SIDE.4.DIMENSION B DOES NOT INCLUDEINTERLEAD FLASH OR PROTRUSION.INTERLEAD FLASH OR PROTRUSION
SHALL NOT EXCEED 0.25 (0.010) PER SIDE.5.DIMENSION K DOES NOT INCLUDEDAMBAR PROTRUSION. ALLOWABLEDAMBAR PROTRUSION SHALL BE 0.08(0.003) TOTAL IN EXCESS OF THE KDIMENSION AT MAXIMUM MATERIALCONDITION.
6.TERMINAL NUMBERS ARE SHOWN FORREFERENCE ONLY.
7.DIMENSION A AND B ARE TO BEDETERMINED AT DATUM PLANE −W−.MILLIMETERSINCHESDIMMINMAXMINMAXA6.406.600.2520.260B4.304.500.1690.177−−−−−−0.047C1.20D0.050.150.0020.006F0.500.750.0200.030G0.65 BSC0.026 BSC−W−H0.270.370.0110.015J0.090.200.0040.008J10.090.160.0040.006K0.190.300.0070.012K10.190.250.0070.010L6.40 BSC0.252 BSCM0 8 0 8 ____0.15 (0.006)TUS0.10 (0.004)MTUSVSKK12XL/22011JJ1LPIN 1IDENT110B−U−NSECTION N−N0.25 (0.010)M0.15 (0.006)TUSA−V−NFDETAIL ECD0.100 (0.004)−T−SEATINGPLANEGHDETAIL ESOLDERING FOOTPRINT*
7.0610.65PITCH
0.36
16X
16X1.26DIMENSIONS: MILLIMETERS*For additional information on our Pb−Free strategy and solderingdetails, please download the ON Semiconductor Soldering andMounting Techniques Reference Manual, SOLDERRM/D.
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MC74HCT244A
PACKAGE DIMENSIONS
SOEIAJ−20F SUFFIXCASE 967−01ISSUE A
2011LEQ1M_LDETAIL PEHE110ZDeAVIEW PcNOTES:
1.DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2.CONTROLLING DIMENSION: MILLIMETER.3.DIMENSIONS D AND E DO NOT INCLUDE
MOLD FLASH OR PROTRUSIONS AND ARE
MEASURED AT THE PARTING LINE. MOLD FLASHOR PROTRUSIONS SHALL NOT EXCEED 0.15(0.006) PER SIDE.
4.TERMINAL NUMBERS ARE SHOWN FOR
REFERENCE ONLY.
5.THE LEAD WIDTH DIMENSION (b) DOES NOT
INCLUDE DAMBAR PROTRUSION. ALLOWABLEDAMBAR PROTRUSION SHALL BE 0.08 (0.003)TOTAL IN EXCESS OF THE LEAD WIDTH
DIMENSION AT MAXIMUM MATERIAL CONDITION.DAMBAR CANNOT BE LOCATED ON THE LOWERRADIUS OR THE FOOT. MINIMUM SPACE
BETWEEN PROTRUSIONS AND ADJACENT LEADTO BE 0.46 ( 0.018).
DIMAA1bcDEeHELLEMQ1ZMILLIMETERSMINMAX−−−2.050.050.200.350.500.150.2512.3512.805.105.451.27 BSC7.408.200.500.851.101.500 _10 _0.700.90−−−0.81INCHESMINMAX−−−0.0810.0020.0080.0140.0200.0060.0100.4860.5040.2010.2150.050 BSC0.2910.3230.0200.0330.0430.0590 _10 _0.0280.035−−−0.032b0.13 (0.005)MA10.10 (0.004)ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further noticeto any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liabilityarising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.“Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. Alloperating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rightsnor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applicationsintended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. ShouldBuyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates,and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or deathassociated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an EqualOpportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.
PUBLICATION ORDERING INFORMATION
LITERATURE FULFILLMENT:Literature Distribution Center for ON SemiconductorP.O. Box 5163, Denver, Colorado 80217 USAPhone: 303−675−2175 or 800−344−3860 Toll Free USA/CanadaFax: 303−675−2176 or 800−344−3867 Toll Free USA/CanadaEmail: orderlit@onsemi.comN. American Technical Support: 800−282−9855 Toll FreeUSA/CanadaEurope, Middle East and Africa Technical Support:Phone: 421 33 790 2910Japan Customer Focus CenterPhone: 81−3−5773−3850ON Semiconductor Website: www.onsemi.comOrder Literature: http://www.onsemi.com/orderlitFor additional information, please contact your localSales Representativehttp://onsemi.com8MC74HCT244A/D
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