Xilinx FPGA实验报告
——十二进制同步计数器
十二进制同步计数器
1．实验内容
1) 用BCD码实现个位和十位 ，其中个位十进制，十位二进制。 2) 当计数到11时，产生进位脉冲。
3) 自行设计VHDL测试向量文件，进行仿真测试。
4) 分频产生1Hz信号，用1Hz信号作为十二进制同步计数器的计数时钟。 5) 设计数码管译码电路，将计数结果在BASYS2实验板上下载显示。
2．实验目的
1) 熟悉Xilinx的ISE软件的使用和设计流程； 2) 掌握ISE仿真方法； 3) 熟悉Xilinx FPGA开发板
4) 利用VHDL语言设计计数器电路，下载到FPGA板上进行验证。
3．实验环境
1) PC机一台；
2) Xilinx的ISE软件一套；
4．实验结果
顶层模块 library IEEE;
use IEEE.STD_LOGIC_1164.ALL; entity top12 is
Port ( clock : in STD_LOGIC; clear : in STD_LOGIC;
segment_4 : out std_logic_vector(3 downto 0);
result : out STD_LOGIC_VECTOR (6 downto 0);
jinwei:out std_logic);
end top12;
architecture Behavioral of top12 is component frequency
Port ( clock : in STD_LOGIC; clock_1Hz : out STD_LOGIC;
clock_1kHz : out STD_LOGIC);
end component;
component counter12 Port ( clock : in STD_LOGIC; clear : in STD_LOGIC;
jinwei:out std_logic;
result : out STD_LOGIC_VECTOR (7 downto 0)); end component; component segment
Port ( bcd1 : in STD_LOGIC_VECTOR (3 downto 0); bcd2 : in STD_LOGIC_VECTOR (3 downto 0); segment_4 : out STD_LOGIC_vector(3 downto 0); result : out STD_LOGIC_VECTOR (6 downto 0); clock : in STD_LOGIC); end component;
signal clock_1Hz: std_logic; signal clock_1kHz: std_logic;
signal bcd1: std_logic_vector(3 downto 0); --个位 signal bcd2: std_logic_vector(3 downto 0); --十位 begin
U0: frequency port
map( clock=>clock,clock_1Hz=>clock_1Hz,clock_1kHz=>clock_1kHz);
U1:counter12 port map(clock=>clock_1Hz,
clear=>clear, jinwei=>jinwei,
result(3 downto 0)=>bcd1, result(7 downto 4)=>bcd2);
U2:segment port map( bcd1 =>bcd1,
bcd2 =>bcd2,
segment_4 =>segment_4, result =>result, clock =>clock_1kHz); end Behavioral; 分频部分： library IEEE;
use IEEE.STD_LOGIC_1164.ALL; use ieee.std_logic_unsigned.all;
entity frequency is
Port ( clock : in STD_LOGIC;
clock_1Hz : out STD_LOGIC;
clock_1kHz : out STD_LOGIC); end frequency;
architecture Behavioral of frequency is
SIGNAL temp_1Hz : STD_LOGIC ; SIGNAL temp_1kHz : STD_LOGIC ;
BEGIN
PROCESS(clock)
VARIABLE cnt : INTEGER RANGE 0 TO 50000000 :=0;
VARIABLE cntt : INTEGER RANGE 0 TO 50000 :=0;
BEGIN
IF (clock'EVENT AND clock='1') THEN--上升沿 cnt := cnt+1;
cntt := cntt+1;
temp_1Hz <= '0'; -- 是否多余 temp_1kHz <= '0';
IF cnt=50000000 THEN cnt := 0;
temp_1Hz <= '1';
END IF;
if (cntt=50000) then
cntt:=0;
temp_1kHz <= '1';
END IF; end if; END PROCESS; clock_1Hz<= temp_1Hz; clock_1kHz <=temp_1kHz; end Behavioral; 计数器部分： LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL; USE IEEE.STD_LOGIC_ARITH.ALL; entity counter12 is
Port ( clock : in STD_LOGIC; clear : in STD_LOGIC;
jinwei:out std_logic;
result : out STD_LOGIC_VECTOR (7 downto 0)); end counter12;
architecture Behavioral of counter12 is
signal temp: std_logic_vector(7 downto 0):=\"00000000\"; begin process(clock) begin
if (clock'event and clock='1') then if (clear='1') then temp <= \"00000000\";
jinwei<='0';
elsif(temp=\"00010001\")then
jinwei<= '1';
temp <=\"00000000\";
elsif(temp=\"00010000\")then jinwei<='0'; temp<=\"00010001\"; elsif(temp=\"00001001\")then jinwei<='0'; temp<=\"00010000\"; elsif(temp<\"00001001\")then temp <= temp+1; jinwei<='0'; else
temp<=\"00000000\"; jinwei<='0';
end if; end if;
end process; result<= temp; end Behavioral; 显示与译码部分： library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity segment is
Port ( bcd1 : in STD_LOGIC_VECTOR (3 downto 0); bcd2 : in STD_LOGIC_VECTOR (3 downto 0);
segment_4 : out STD_LOGIC_vector(3 downto 0):=\"1111\"; result : out STD_LOGIC_VECTOR (6 downto 0); clock : in STD_LOGIC); end segment;
architecture Behavioral of segment is
signal count: std_logic := '0' ;
signal bcd_in: std_logic_vector(3 downto 0);
begin
process(clock) begin
if (clock'event and clock='1') then--上升沿
if(count = '0') then
bcd_in <= bcd1;--个位 segment_4<=\"1110\";-- count <='1';
else
bcd_in <= bcd2;--十位 segment_4<=\"1101\"; count <= '0';
end if;
end if; end process;
process(bcd_in) begin
case bcd_in is
when \"0000\"=> result <= \"1000000\"; when \"0001\"=> result <= \"1111001\"; when \"0010\"=> result <= \"0100100\"; when \"0011\"=> result <= \"0110000\"; when \"0100\"=> result <= \"0011001\"; when \"0101\"=> result <= \"0010010\"; when \"0110\"=> result <= \"0000010\"; when \"0111\"=> result <= \"1111000\"; when \"1000\"=> result <= \"0000000\"; when \"1001\"=> result <= \"0010000\"; when others=> null;
end case;
end process;
end Behavioral;
5．实验总结
为了便于正确得完成整个工程的任务，应该先对每个模块进行仿真测试，然后再进行整体的调试。这样才能准确的找到程序的错误，提高效率。通过这次实验，提高了调试的能力，了解了计数器和数码管的译码和显示的工作原理。
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