1）仿真程序： entity MUXK is
port(a1,a2,a3,sQ,s1: in bit; outy:out bit); end entity MUXK;
architecture one of MUXK is signal tmp:bit; begin
PRO1:process(sQ,a2,a3) begin
case sQ is
when '0'=>tmp<=a2; when '1'=>tmp<=a3; end case; end process;
PRO2:process(a1,tmp,s1) begin
case s1 is
when '0'=>outy<=a1; when '1'=>outy<=tmp; end case; end process;
end architecture one;
2）仿真结果：
3）电路图：
4.4
1）仿真程序： D触发器程序 library ieee;
use ieee.std_logic_1164.all; entity DFF1 is
port(a:in std_logic; D:in std_logic; Q:out std_logic); end;
architecture bhv of DFF1 is signal Q1:std_logic; begin
process(a) begin
if a'event and a='1' then Q1<=D; end if; Q<=Q1;
end process; end bhv; 最终程序
library ieee;
use ieee.std_logic_1164.all; entity dcfq is
port (CL,CLK0:in std_logic; OUT1:out std_logic); end entity dcfq;
architecture dc of dcfq is component DFF1
port(a:in std_logic; D:in std_logic; Q:out std_logic);
end component;
signal e,f:std_logic; begin
u1:DFF1 port map(D=>f,Q=>e,a=>CLK0); process(e) begin
f<=not (CL or e); e<=e;
OUT1<=not e; end process;
end architecture dc;
2）仿真结果：
3）电路图： D触发器封装图
最终电路图
4.5
1.1）仿真程序：
library ieee;
use ieee.std_logic_1164.all; entity h_suber is
port (x,y:in std_logic; diff,s_out:out std_logic); end entity h_suber ;
architecture sh1 of h_suber is
signal xyz,cso: std_logic_vector(1 downto 0); begin
xyz<=x&y;diff<=cso(1);s_out<=cso(0); process(xyz) begin
case xyz is
when\"00\"=>cso<=\"00\"; when\"01\"=>cso<=\"11\"; when\"10\"=>cso<=\"10\"; when\"11\"=>cso<=\"00\"; end case; end process;
end architecture sh1;
1.2）仿真结果：
1.3）电路图：
2.1）仿真程序：
library ieee;
use ieee.std_logic_1164.all; entity f_suber is
port (xin,yin,sub_in:in std_logic; diffr,sub_out:out std_logic); end entity f_suber;
architecture fd1 of f_suber is component h_suber
port (x,y:in std_logic; diff,s_out:out std_logic); end component;
signal d,e,f:std_logic; begin
u1:h_suber port map(x=>xin,y=>yin,diff=>d,s_out=>e);
u2:h_suber port map(x=>d,y=>sub_in,diff=>diffr,s_out=>f); sub_out<=e or f;
end architecture fd1;
2.2）仿真结果：
2.3）电路图：
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