IS61LF102418A-7.5B2I资料

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IS61LF25672AIS61VF25672AIS61LF51236AIS61VF51236AIS61LF102418A IS61VF102418A256K x 72, 512K x 36, 1024K x 18

18Mb SYNCHRONOUS FLOW-THROUGHSTATIC RAM

ISSI

APRIL 2006

FEATURES

•Internal self-timed write cycle

•Individual Byte Write Control and Global Write•Clock controlled, registered address, data andcontrol•Burst sequence control using MODE input•Three chip enable option for simple depth expan-sion and address pipelining•Common data inputs and data outputs•Auto Power-down during deselect•Single cycle deselect

•Snooze MODE for reduced-power standby•JTAG Boundary Scan for PBGA package•Power Supply

LF: VDD 3.3V + 5%, VDDQ 3.3V/2.5V + 5%VF: VDD 2.5V + 5%, VDDQ 2.5V + 5%•JEDEC 100-Pin TQFP, 119-pin PBGA, 209-BallPBGA and 165-pin PBGA packages.•Lead-free available

DESCRIPTION

TheISSIIS61LF/VF25672A, IS61LF/VF51236A and

IS61LF/VF102418A are high-speed, low-power synchro-nous static RAMs designed to provide burstable, high-performance memory for communication and networkingapplications. The IS61LF/VF25672A is organized as262,144 words by 72 bits. The IS61LF/VF51236A is orga-nized as 524,288 words by 36 bits. The IS61LF/VF102418Ais organized as 1,048,576 words by 18 bits. Fabricatedwith ISSI's advanced CMOS technology, the device inte-grates a 2-bit burst counter, high-speed SRAM core, andhigh-drive capability outputs into a single monolithic cir-cuit. All synchronous inputs pass through registers con-trolled by a positive-edge-triggered single clock input.Write cycles are internally self-timed and are initiated bythe rising edge of the clock input. Write cycles can be oneto four bytes wide as controlled by the write control inputs.Separate byte enables allow individual bytes to be written.Byte write operation is performed by using byte writeenable (BWE) input combined with one or more individualbyte write signals (BWx). In addition, Global Write (GW) isavailable for writing all bytes at one time, regardless of thebyte write controls.

Bursts can be initiated with either ADSP (Address StatusProcessor) or ADSC (Address Status Cache Controller)input pins. Subsequent burst addresses can be generatedinternally and controlled by the ADV (burst address ad-vance) input pin.

The mode pin is used to select the burst sequence order,Linear burst is achieved when this pin is tied LOW.Interleave burst is achieved when this pin is tied HIGH orleft floating.

FAST ACCESS TIME

SymboltKQtKC

Parameter

Clock Access TimeCycle TimeFrequency

-6.56.57.5133

-7.57.58.5117

UnitsnsnsMHz

Copyright © 2006 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any timewithout notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised toobtain the latest version of this device specification before relying on any published information and before placing orders for products.

Integrated Silicon Solution, Inc. — 1-800-379-4774Rev.E04/21/06

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IS61LF25672A IS61LF51236A IS61LF102418AIS61VF25672A IS61VF51236A IS61VF102418A

BLOCK DIAGRAM

MODECLKCLKQ0A0A0'ISSI

BINARYCOUNTERADVADSCADSPCECLRQ1A1A1'256Kx72;512Kx36; 1024Kx18MEMORY ARRAY19/2019/20ADQ17/18ADDRESSREGISTERCECLK36,or 18or 7236,or 18or 72GWBWEBW(a-h)x18: a,bx36: a-dx72: a-hDQ(a-h)BYTE WRITEREGISTERSCLKDQCECE2CE2DQ2/4/8ENABLEREGISTERCECLKINPUTREGISTERSCLKOE36,or 18or 72DQa - DQdDQENABLEDELAYREGISTERCLKOE2Integrated Silicon Solution, Inc. — 1-800-379-4774Rev.E04/21/06

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IS61LF25672A IS61LF51236A IS61LF102418AIS61VF25672A IS61VF51236A IS61VF102418A

165-PIN BGA

165-Ball, 13x15 mm BGA

ISSI

119-PIN BGA

119-Ball, 14x22 mm BGA

BOTTOM VIEWBOTTOM VIEW209-BALL BGA

209-Ball, 14 mm x 22 mm BGA1 mm Ball Pitch, 11 x 19 Ball Array

BOTTOM VIEWIntegrated Silicon Solution, Inc. — 1-800-379-4774Rev.E04/21/06

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IS61LF25672A IS61LF51236A IS61LF102418AIS61VF25672A IS61VF51236A IS61VF102418A

PIN CONFIGURATION — 256K X 72, 209-Ball PBGA (TOP VIEW)

12345678ABCDEFGHJKLMNPRTUVW

DQgDQgDQgDQgDQPgDQcDQcDQcDQcNCDQhDQhDQhDQhDQPdDQdDQdDQdDQd

DQgDQgDQgDQgDQPcDQcDQcDQcDQcNCDQhDQhDQhDQhDQPhDQdDQdDQdDQd

ABWcBWhVSSVDDQVSSVDDQVSSVDDQCLKVDDQVSSVDDQVSSVDDQVSSNCATMS

CE2BWgBWdNCVDDQVSSVDDQVSSVDDQNCVDDQVSSVDDQVSSVDDQNCAATDI

ADSPNCNCNCVDDVSSVDDVSSVDDVSSVDDVSSVDDVSSVDDNCAAA

ADSCBWECEOEVDDNCNCNCNCNCNCNCNCZZVDDMODEAA1A0

ADVANCGWVDDVSSVDDVSSVDDVSSVDDVSSVDDVSSVDDNCAAA

CE2BWbBWeNCVDDQVSSVDDQVSSVDDQNCVDDQVSSVDDQVSSVDDQNCAATDO

ISSI

ABWfBWaVSSVDDQVSSVDDQVSSVDDQNCVDDQVSSVDDQVSSVDDQVSSNCATCK

DQbDQbDQbDQbDQPfDQfDQfDQfDQfNCDQaDQaDQaDQaDQPaDQeDQeDQeDQe

DQbDQbDQbDQbDQPbDQfDQfDQfDQfNCDQaDQaDQaDQaDQPeDQeDQeDQeDQe

11 x 19 Ball BGA—14 x 22 mm2 Body—1 mm Ball Pitch

PIN DESCRIPTIONS

Symbol

AA0, A1ADVADSPADSCGWCLK

CE, CE2, CE2BWx (x=a,b,c,d e,f,g,h)

Pin Name

Address Inputs

Synchronous Burst Address InputsSynchronous Burst AddressAdvance

Address Status ProcessorAddress Status ControllerGlobal Write EnableSynchronous ClockSynchronous Chip SelectSynchronous Byte WriteControls

SymbolBWEOEZZMODETCK, TDOTMS, TDINCDQxDQPxVDDVDDQ

Vss

Pin NameByte Write EnableOutput EnablePower Sleep ModeBurst Sequence SelectionJTAG Pins

No Connect

Data Inputs/OutputsData Inputs/Outputs3.3V/2.5V Power Supply

Isolated Output Power Supply3.3V/2.5VGround

4Integrated Silicon Solution, Inc. — 1-800-379-4774Rev.E04/21/06

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IS61LF25672A IS61LF51236A IS61LF102418AIS61VF25672A IS61VF51236A IS61VF102418A

119 BGA PACKAGE PIN CONFIGURATION-512K X 36 (TOP VIEW)

ABCDEFGHJKLMNPRTU

VDDQNCNCDQcDQcVDDQDQcDQcVDDQDQdDQdVDDQDQdDQdNCNCVDDQ

2AAADQPcDQcDQcDQcDQcVDDDQdDQdDQdDQdDQPdANCTMS

3AAAVssVssVssBWcVssNCVssBWdVssVssVssMODEATDI

4ADSPADSCVDDNCCEOEADVGWVDDCLKNCBWEA1*A0*VDDATCK

5AAAVssVssVssBWbVssNCVssBWaVssVssVssNCATDO

ISSI

AVDDQA NCA NCDQPb DQbDQb DQbDQb VDDQDQb DQbDQb DQbVDD VDDQDQa DQaDQaDQaDQaDQPaANCNC

DQa VDDQ DQa DQa NC ZZ VDDQ

Note: * A0 and A1 are the two least significant bits (LSB) of the address field and set the internal burst counter if burst is desired.

PIN DESCRIPTIONS

SymbolAA0, A1ADVADSPADSCGWCLKCEBWE

Pin Name

Address Inputs

Synchronous Burst Address InputsSynchronous Burst AddressAdvance.

Address Status ProcessorAddress Status ControllerGlobal Write EnableSynchronous ClockSynchronous Chip SelectByte Write Enable

SymbolOEZZMODETCK, TDO TMS, TDINC

DQa-DQdDQPa-PdVDDVDDQVss

Pin NameOutput Enable

Power Sleep Mode

Burst Sequence SelectionJTAG Pins

No Connect

Data Inputs/OutputsData Inputs/OutputsPower Supply

Output Power SupplyGround

BWx (x=a-d)Synchronous Byte Write Controls

Integrated Silicon Solution, Inc. — 1-800-379-4774Rev.E04/21/06

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IS61LF25672A IS61LF51236A IS61LF102418AIS61VF25672A IS61VF51236A IS61VF102418A

ISSI

119 BGA PACKAGE PIN CONFIGURATION1MX18 (TOP VIEW)

ABCDEFGHJKLMNPRTU

VDDQNCNCDQbNCVDDQNCDQbVDDQNCDQbVDDQDQbNCNCNCVDDQ

2AAANCDQbNCDQbNCVDDDQbNCDQbNCDQPbAATMS

3AAAVssVssVssBWbVssNCVssVssVssVssVssMODEATDI

4ADSPADSCVDDNCCEOEADVGWVDDCLKNCBWEA1*A0*VDDNCTCK

5AAAVssVssVssVssVssNCVssBWaVssVssVssNCATDO

AVDDQA NCA NCDQPa NCNC DQaDQa VDDQNC DQaDQa NCVDD VDDQNC DQaDQa NCNC VDDQDQa NCNC DQaA NCA ZZ NC VDDQ

Note: * A0 and A1 are the two least significant bits (LSB) of the address field and set the internal burst counter if burst is desired.

PIN DESCRIPTIONS

Symbol

AA0, A1ADVADSPADSCGWCLKCEBWE

Pin Name

Address Inputs

Synchronous Burst Address InputsSynchronous Burst AddressAdvance.

Address Status ProcessorAddress Status ControllerGlobal Write EnableSynchronous ClockSynchronous Chip SelectByte Write Enable

SymbolOEZZMODETCK, TDOTMS, TDINC

DQa-DQbDQPa-PbVDDVDDQVss

Pin NameOutput Enable

Power Sleep Mode

Burst Sequence SelectionJTAG Pins

No Connect

Data Inputs/OutputsData Inputs/OutputsPower Supply

Output Power SupplyGround

BWx (x=a,b)Synchronous Byte Write Controls

6Integrated Silicon Solution, Inc. — 1-800-379-4774Rev.E04/21/06

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IS61LF25672A IS61LF51236A IS61LF102418AIS61VF25672A IS61VF51236A IS61VF102418A

ISSI

8ADSCOEVssVDDVDDVDDVDDVDDVDDVDDVDDVDDVssAA

9ADVADSPVDDQVDDQVDDQVDDQVDDQNCVDDQVDDQVDDQVDDQVDDQAA

10AADQbDQbDQbDQbNCDQaDQaDQaDQaAA

11NCNCDQbDQbDQbDQbZZDQaDQaDQaDQaAA

165 PBGA PACKAGE PIN CONFIGURATION

512K X 36 (TOP VIEW)

1ABCDEFGHJKLMNPR

NCNCDQPcDQcDQcDQcDQcNCDQdDQdDQdDQdDQPdNCMODE

2AANCDQcDQcDQcDQcVssDQdDQdDQdDQdNCNCNC

3CECE2VDDQVDDQVDDQVDDQVDDQNCVDDQVDDQVDDQVDDQVDDQAA

4BWcBWdVssVDDVDDVDDVDDVDDVDDVDDVDDVDDVssAA

5BWbBWaVssVssVssVssVssVssVssVssVssVssNCTDITMS

6CE2CLKVssVssVssVssVssVssVssVssVssVssAA1*A0*

7BWEGWVssVssVssVssVssVssVssVssVssVssVssTDOTCK

NC DQPb

NC DQPa

Note: * A0 and A1 are the two least significant bits (LSB) of the address field and set the internal burst counter if burst is desired.

PIN DESCRIPTIONS

SymbolAA0, A1ADVADSPADSCGWCLK

CE, CE2, CE2

Pin Name

Address Inputs

Synchronous Burst AddressInputs

Synchronous Burst AddressAdvance.

Address Status ProcessorAddress Status ControllerGlobal Write EnableSynchronous ClockSynchronous Chip Select

SymbolBWEOEZZMODETCK, TDOTMS, TDINC

DQa-DQdDQPa-PdVDDVDDQ

Vss

Pin NameByte Write EnableOutput EnablePower Sleep ModeBurst Sequence SelectionJTAG Pins

No Connect

Data Inputs/OutputsData Inputs/OutputsPower Supply

Output Power SupplyGround

BWx (x=a,b,c,d)Synchronous Byte Write

Controls

Integrated Silicon Solution, Inc. — 1-800-379-4774Rev.E04/21/06

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IS61LF25672A IS61LF51236A IS61LF102418AIS61VF25672A IS61VF51236A IS61VF102418A

165 PBGA PACKAGE PIN CONFIGURATION

1M X 18 (TOP VIEW)

ABCDEFGHJKLMNPR

NCNCNCNCNCNCNCNCDQbDQbDQbDQbDQPbNCMODE

2AANCDQbDQbDQbDQbVssNCNCNCNCNCNCNC

3CECE2VDDQVDDQVDDQVDDQVDDQNCVDDQVDDQVDDQVDDQVDDQAA

4BWbNCVssVDDVDDVDDVDDVDDVDDVDDVDDVDDVssAA

5NCBWaVssVssVssVssVssVssVssVssVssVssNCTDITMS

6CE2CLKVssVssVssVssVssVssVssVssVssVssAA1*A0*

7BWEGWVssVssVssVssVssVssVssVssVssVssVssTDOTCK

8ADSCOEVssVDDVDDVDDVDDVDDVDDVDDVDDVDDVssAA

9ADVADSPVDDQVDDQVDDQVDDQVDDQNCVDDQVDDQVDDQVDDQVDDQAA

10AANCNCNCNCNCNCDQaDQaDQaDQaNCAA

ISSI

11ANCDQPaDQaDQaDQaDQaZZNCNCNCNCNCAA

Note: * A0 and A1 are the two least significant bits (LSB) of the address field and set the internal burst counter if burst is desired.

PIN DESCRIPTIONS

SymbolAA0, A1ADVADSPADSCGWCLK

CE, CE2, CE2BWx (x=a,b)

Pin Name

Address Inputs

Synchronous Burst AddressInputs

Synchronous Burst AddressAdvance.

Address Status ProcessorAddress Status ControllerGlobal Write EnableSynchronous ClockSynchronous Chip SelectSynchronous Byte WriteControls

SymbolBWEOEZZMODETCK, TDOTMS, TDINC

DQa-DQdDQPa-PdVDDVDDQ

Vss

Pin Name

Byte Write EnableOutput EnablePower Sleep ModeBurst Sequence SelectionJTAG Pins

No Connect

Data Inputs/OutputsData Inputs/OutputsPower Supply

Output Power SupplyGround

8Integrated Silicon Solution, Inc. — 1-800-379-4774Rev.E04/21/06

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IS61LF25672A IS61LF51236A IS61LF102418AIS61VF25672A IS61VF51236A IS61VF102418A

PIN CONFIGURATION

100-Pin TQFP

AACECE2BWdBWcBWbBWaCE2VDDVSSCLKGWBWEOEADSCADSPADVAAISSI

DQPcDQcDQcVDDQVSSDQcDQcDQcDQcVSSVDDQDQcDQcNCVDDNCVSSDQdDQdVDDQVSSDQdDQdDQdDQdVSSVDDQDQdDQdDQPd100999897969594939291908988878685848382818017927837747657567477387297110701169121368146715661665176418631962206121602259235824572556265527542853295230513132333435363738394041424344454647484950DQPbDQbDQbVDDQVSSDQbDQbDQbDQbVSSVDDQDQbDQbVSSNCVDDZZDQaDQaVDDQVSSDQaDQaDQaDQaVSSVDDQDQaDQaDQPa PIN DESCRIPTIONS

A0, A1

Synchronous Address Inputs. Thesepins must tied to the two LSBs of theaddress bus.

Synchronous Address InputsSynchronous Controller Address StatusSynchronous Processor Address StatusSynchronous Burst Address AdvanceSynchronous Byte Write EnableSynchronous Byte Write EnableSynchronous Clock

Synchronous Data Input/Output

DQPa-DQPdVssGWMODEOETMS, TDI,TCK, TDOVDDVDDQZZ

Parity Data Input/OutputGround

Synchronous Global Write EnableBurst Sequence Mode SelectionOutput Enable

JTAG Boundary Scan Pins3.3V/2.5V Power SupplyIsolated Output Buffer Supply:3.3V/2.5VSnooze Enable

AADSCADSPADVBWa-BWdBWECLKDQa-DQd

CE, CE2, CE2Synchronous Chip Enable

Integrated Silicon Solution, Inc. — 1-800-379-4774Rev.E04/21/06

MODEAAAAA1A0NCNCVSSVDDAAAAAAAAA512K x 36元器件交易网www.cecb2b.com

IS61LF25672A IS61LF51236A IS61LF102418AIS61VF25672A IS61VF51236A IS61VF102418A

PIN CONFIGURATION

100-Pin TQFP

AACECE2NCNCBWbBWaCE2VDDVSSCLKGWBWEOEADSCADSPADVAAISSI

10099989796959493929190898887868584838281NCNCNCVDDQVSSNCNCDQbDQbVSSVDDQDQbDQbNCVDDNCVSSDQbDQbVDDQVSSDQbDQbDQPbNCVSSVDDQNCNCNC1234567891011121314151617181920212223242526272829303132333435363738394041424344454647484950MODEAAAAA1A0NCNCVSSVDDAAAAAAAAA807978777675747372717069686766656463626160595857565554535251ANCNCVDDQVSSNCDQPaDQaDQaVSSVDDQDQaDQaVSSNCVDDZZDQaDQaVDDQVSSDQaDQaNCNCVSSVDDQNCNCNC1024K x 18PIN DESCRIPTIONS

A0, A1

Synchronous Address Inputs. Thesepins must tied to the two LSBs of theaddress bus.

Synchronous Data Input/Output

DQPa-DQPbVSSGWMODEOETMS, TDI,TCK, TDOVDDVDDQ

Parity Data I/O; DQPa is parity forDQa1-8; DQPb is parity for DQb1-8Ground

Synchronous Global Write EnableBurst Sequence Mode SelectionOutput Enable

JTAG Boundary Scan Pins3.3V/2.5V Power SupplyIsolated Output Buffer Supply:3.3V/2.5VSnooze Enable

AADSCADSPADVBWa-BWbBWECLKDQa-DQb

CE, CE2, CE2Synchronous Chip Enable

10Integrated Silicon Solution, Inc. — 1-800-379-4774Rev.E04/21/06

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IS61LF25672A IS61LF51236A IS61LF102418AIS61VF25672A IS61VF51236A IS61VF102418A

TRUTH TABLE(1-8)(3CE option)

OPERATIONDeselect Cycle, Power-DownDeselect Cycle, Power-DownDeselect Cycle, Power-DownDeselect Cycle, Power-DownDeselect Cycle, Power-DownSnooze Mode, Power-DownRead Cycle, Begin BurstRead Cycle, Begin BurstWrite Cycle, Begin BurstRead Cycle, Begin BurstRead Cycle, Begin BurstRead Cycle, Continue BurstRead Cycle, Continue BurstRead Cycle, Continue BurstRead Cycle, Continue BurstWrite Cycle, Continue BurstWrite Cycle, Continue BurstRead Cycle, Suspend BurstRead Cycle, Suspend BurstRead Cycle, Suspend BurstRead Cycle, Suspend BurstWrite Cycle, Suspend BurstWrite Cycle, Suspend BurstADDRESSNoneNoneNoneNoneNoneNoneExternalExternalExternalExternalExternalNextNextNextNextNextNextCurrentCurrentCurrentCurrentCurrentCurrentCEHLLLLXLLLLLXXHHXHXXHHXHCE2XXHXHXLLLLLXXXXXXXXXXXXCE2XLXLXXHHHHHXXXXXXXXXXXXZZLLLLLHLLLLLLLLLLLLLLLLLADSPADSCADVWRITEXLLHHXLLHHHHHXXHXHHXXHXLXXLLXXXLLLHHHHHHHHHHHHXXXXXXXXXXXLLLLLLHHHHHHXXXXXXXXLHHHHHHLLHHHHLLOEXXXXXXLHXLHLHLHXXLHLHXXISSI

CLKL-HL-HL-HL-HL-HXL-HL-HL-HL-HL-HL-HL-HL-HL-HL-HL-HL-HL-HL-HL-HL-HL-HDQ®

High-ZHigh-ZHigh-ZHigh-ZHigh-ZHigh-ZQHigh-ZDQHigh-ZQHigh-ZQHigh-ZDDQHigh-ZQHigh-ZDDNOTE:

1.X means “Don’t Care.” H means logic HIGH. L means logic LOW.

2.For WRITE, L means one or more byte write enable signals (BWa-h) and BWE are LOW or GW is LOW. WRITE = H for allBWx, BWE, GW HIGH.

3.BWa enables WRITEs to DQa’s and DQPa. BWb enables WRITEs to DQb’s and DQPb. BWc enables WRITEs to DQc’sandDQPc. BWd enables WRITEs to DQd’s and DQPd. BWe enables WRITEs to DQe’s and DQPe. BWf enables WRITEs to DQf’sand DQPf. BWg enables WRITEs to DQg’s and DQPg. BWh enables WRITEs to DQh’s and DQPh. DQPa-DQPh are availableon the x72 version. DQPa and DQPb are available on the x18 version.DQPa-DQPd are available on the x36 version.4.All inputs except OE and ZZ must meet setup and hold times around the rising edge (LOW to HIGH) of CLK.5.Wait states are inserted by suspending burst.

6.For a WRITE operation following a READ operation, OE must be HIGH before the input data setup time and held HIGH duringthe input data hold time.

7.This device contains circuitry that will ensure the outputs will be in High-Z during power-up.

8.ADSP LOW always initiates an internal READ at the L-H edge of CLK. A WRITE is performed by setting one or more byte writeenable signals and BWE LOW or GW LOW for the subsequent L-H edge of CLK. See WRITE timing diagram for clarification.

Integrated Silicon Solution, Inc. — 1-800-379-4774Rev.E04/21/06

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IS61LF25672A IS61LF51236A IS61LF102418AIS61VF25672A IS61VF51236A IS61VF102418A

TRUTH TABLE(1-8)(1CE option)

NEXT CYCLEDeselectedRead, Begin BurstRead, Begin BurstWrite, Begin BurstRead, Begin BurstRead, Begin BurstRead, Continue BurstRead, Continue BurstRead, Continue BurstRead, Continue BurstWrite, Continue BurstWrite, Continue BurstRead, Suspend BurstRead, Suspend BurstRead, Suspend BurstRead, Suspend BurstWrite, Suspend BurstWrite, Suspend Burst

ADDRESSCENoneExternalExternalExternalExternalExternalNextNextNextNextNextNextCurrentCurrentCurrentCurrentCurrentCurrent

HLLLLLXXHHXHXXHHXH

ADSPXLLHHHHHXXHXHHXXHX

ADSCLXXLLLHHHHHHHHHHHH

ADVXXXXXXLLLLLLHHHHHH

WRITEXXXLHHHHHHLLHHHHLL

ISSI

OEXLHXLHLHLHXXLHLHXX

DQHigh-ZQHigh-ZDQHigh-ZQHigh-ZQHigh-ZDDQHigh-ZQHigh-ZDD

NOTE:

1.X means “Don’t Care.” H means logic HIGH. L means logic LOW.

2.For WRITE, L means one or more byte write enable signals (BWa-h) and BWE are LOW or GW is LOW. WRITE = H for allBWx, BWE, GW HIGH.

6.For a WRITE operation following a READ operation, OE must be HIGH before the input data setup time and held HIGH duringthe input data hold time.

7.This device contains circuitry that will ensure the outputs will be in High-Z during power-up.

PARTIAL TRUTH TABLE

FunctionReadRead

Write Byte 1Write All BytesWrite All Bytes

GWHHHHL

BWEHLLLX

BWaXHLLX

BWbXHHLX

BWcXHHLX

BWdXHHLX

BWeXHHLX

BWfXHHLX

BWgXHHLX

BWhXHHLX

12Integrated Silicon Solution, Inc. — 1-800-379-4774Rev.E04/21/06

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IS61LF25672A IS61LF51236A IS61LF102418AIS61VF25672A IS61VF51236A IS61VF102418A

INTERLEAVED BURST ADDRESS TABLE (MODE = VDD or No Connect)

External Address

A1A0

00011011

1st Burst Address

A1A0

01001110

2nd Burst Address

A1A0

10110001

3rd Burst Address

A1A0

11100100

ISSI

LINEAR BURST ADDRESS TABLE (MODE = VSS)

0,0A1', A0' = 1,10,11,0ABSOLUTE MAXIMUM RATINGS(1)

SymbolTSTGPDIOUT

VIN, VOUTVINVDD

Parameter

Storage TemperaturePower Dissipation

Output Current (per I/O)

Voltage Relative to Vss for I/O PinsVoltage Relative to Vss forfor Address and Control InputsVoltage on VDD Supply Relative to Vss

ValueUnit–55 to +150°C

1.6W100mA

–0.5 to VDDQ + 0.5V–0.5 to VDD + 0.5V

–0.5 to 4.6

Notes:

1.Stress greater than those listed under ABSOLUTE MAXIMUM RATINGS may causepermanent damage to the device. This is a stress rating only and functional operation of thedevice at these or any other conditions above those indicated in the operational sections ofthis specification is not implied. Exposure to absolute maximum rating conditions for extendedperiods may affect reliability.

2. This device contains circuity to protect the inputs against damage due to high static voltagesor electric fields; however, precautions may be taken to avoid application of any voltage higherthan maximum rated voltages to this high-impedance circuit.

3. This device contains circuitry that will ensure the output devices are in High-Z at power up.

Integrated Silicon Solution, Inc. — 1-800-379-4774Rev.E04/21/06

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IS61LF25672A IS61LF51236A IS61LF102418AIS61VF25672A IS61VF51236A IS61VF102418A

OPERATING RANGE (IS61LFxxxxx)

Range

CommercialIndustrial

Ambient Temperature

0°C to +70°C-40°C to +85°C

VDD

3.3V ± 5%3.3V ± 5%

VDDQ

3.3V/2.5V ± 5%3.3V/2.5V ± 5%

ISSI

OPERATING RANGE (IS61VFxxxxx)

Range

CommercialIndustrial

Ambient Temperature

0°C to +70°C-40°C to +85°C

VDD

2.5V ± 5%2.5V ± 5%

VDDQ 2.5V ± 5%2.5V ± 5%

DC ELECTRICAL CHARACTERISTICS (Over Operating Range)3.3VSymbolVOHVOLVIHVILILIILOParameterOutput HIGH VoltageOutput LOW VoltageInput HIGH VoltageInput LOW VoltageInput Leakage CurrentOutput Leakage CurrentVSS ≤ VIN ≤ VDD(1)VSS ≤ VOUT ≤ VDDQ, OE = VIHTest ConditionsIOH = –4.0 mA(3.3V)IOH = –1.0 mA(2.5V)IOL = 8.0 mA(3.3V)IOL = 1.0 mA(2.5V)Min.2.4—2.0–0.3–5–5Max.—0.4VDD + 0.30.855Min.2.0—1.7–0.3–5–52.5VMax.—0.4VDD + 0.30.755UnitVVVVµAµANote:

1.VIL (min.) = –2.0V AC (pulse width - 2.0 ns). Not 100% tested.

VIH (max.) = VDD + 2.0V AC (pulse width - 2.0 ns). Not 100% tested.

POWER SUPPLY CHARACTERISTICS(1) (Over Operating Range)

6.5 MAXx18x362502752502757.5MAXx18x36240250240250SymbolParameterICCAC OperatingSupply CurrentTest ConditionsTemp. rangex72300350UnitmADevice Selected,Com.OE = VIH, ZZ ≤ VIL,Ind. All Inputs ≤ 0.2V or ≥ VDD – 0.2V,Cycle Time ≥ tKC min.Device Deselected,VDD = Max.,All Inputs ≤ VIL or ≥ VIH,ZZ ≤ VIL, f = Max.Device Deselected,VDD = Max.,VIN ≤ VSS + 0.2V or ≥VDD – 0.2V f = 0ZZ>VIHCom.Ind.ISBStandby CurrentTTL Input140150140150140150140150140150mAISBIStandby CurrentCMOS InputCom.Ind.110125110125110125110125110125mAISB2Sleep ModeCom.Ind.60756075607560756075mANote:

1.MODE pin has an internal pullup and should be tied to VDD or VSS. It exhibits ±100 µA maximum leakage current when tied to ≤VSS + 0.2V or ≥ VDD – 0.2V.

14Integrated Silicon Solution, Inc. — 1-800-379-4774Rev.E04/21/06

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IS61LF25672A IS61LF51236A IS61LF102418AIS61VF25672A IS61VF51236A IS61VF102418A

CAPACITANCE(1,2)

SymbolCINCOUT

ParameterInput CapacitanceInput/Output Capacitance

ConditionsVIN = 0VVOUT = 0V

Max.68

UnitpFpF

ISSI

Notes:

1.Tested initially and after any design or process changes that may affect these parameters.2.Test conditions: TA = 25°C, f = 1 MHz, VDD = 3.3V.

3.3V I/O AC TEST CONDITIONS

Parameter

Input Pulse Level

Input Rise and Fall TimesInput and Output Timingand Reference LevelOutput Load

Unit0V to 3.0V1.5 ns1.5VSee Figures 1 and 2

AC TEST LOADS

317 Ω ZO = 50ΩOUTPUT50Ω3.3VOUTPUT5 pFIncludingjig andscopeFigure 2

351 Ω1.5VFigure 1

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IS61LF25672A IS61LF51236A IS61LF102418AIS61VF25672A IS61VF51236A IS61VF102418A

2.5V I/O AC TEST CONDITIONS

Parameter

Input Pulse Level

Input Rise and Fall TimesInput and Output Timingand Reference LevelOutput Load

Unit0V to 2.5V1.5 ns1.25VSee Figures 3 and 4

ISSI

2.5V I/O OUTPUT LOAD EQUIVALENT

1,667 Ω ZO = 50ΩOUTPUT+2.5VOUTPUT50Ω1,538 Ω1.25V5 pFIncludingjig andscopeFigure 3Figure 4

16Integrated Silicon Solution, Inc. — 1-800-379-4774Rev.E04/21/06

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IS61LF25672A IS61LF51236A IS61LF102418AIS61VF25672A IS61VF51236A IS61VF102418A

READ/WRITE CYCLE SWITCHING CHARACTERISTICS(1) (Over Operating Range)

SymbolfmaxtKCtKHtKLtKQtKQX(2)tKQLZ(2,3)tKQHZ(2,3)tOEQtOELZ(2,3)tOEHZ(2,3)tAStWStCEStAVStDStAHtWHtCEHtAVHtDHtPDStPUSNotes:

1.Configuration signal MODE is static and must not change during normal operation.2.Guaranteed but not 100% tested. This parameter is periodically sampled.3.Tested with load in Figure 2.

ISSI

7.5

Min.Max.—8.52.52.5—2.52.5——0—1.51.51.51.51.50.50.50.50.50.5——

117———7.5——4.03.4—3.5——————————22

UnitMHznsnsnsnsnsnsnsnsnsnsnsnsnsnsnsnsnsnsnsnscyccyc

ParameterClock FrequencyCycle TimeClock High TimeClock Low TimeClock Access TimeClock High to Output InvalidClock High to Output Low-ZClock High to Output High-ZOutput Enable to Output ValidOutput Enable to Output Low-ZOutput Disable to Output High-ZAddress Setup TimeRead/Write Setup TimeChip Enable Setup TimeAddress Advance Setup TimeData Setup TimeAddress Hold TimeWrite Hold TimeChip Enable Hold TimeAddress Advance Hold TimeData Hold TimeZZ High to Power DownZZ Low to Power Down

6.5Min.Max.—7.52.22.2—2.52.5——0—1.51.51.51.51.50.50.50.50.50.5——

133———6.5——3.83.2—3.5——————————22

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READ/WRITE CYCLE TIMING

tKCISSI

CLKtSStSHtKHtKLADSP is blocked by CE inactiveADSPtSStSHADSCADVtAStAHAddressRD1tWStWHWR1RD2RD3GWtWStWHBWEtWStWHBWd-BWatCEStCEHWR1CE Masks ADSPCEtCEStCEHCE2 and CE2 only sampled with ADSP or ADSCCE2tCEStCEHUnselected with CE2CE2tOEHZOEtOEQXtKQXDATAOUTHigh-ZtKQLZtKQ1atKQXtKQHZ2a2b2c2dtKQHZDATAINHigh-ZtDS1atDHSingle ReadFlow-throughSingle WriteBurst ReadUnselected18Integrated Silicon Solution, Inc. — 1-800-379-4774Rev.E04/21/06

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IS61LF25672A IS61LF51236A IS61LF102418AIS61VF25672A IS61VF51236A IS61VF102418A

WRITE CYCLE TIMING

tKCISSI

CLKtSStSHtKHtKLADSP is blocked by CE1 inactiveADSC initiate WriteADSPADSCADV must be inactive for ADSP WritetAVSADVtAStAHtAVHAddressWR1tWStWHWR2WR3GWtWStWHBWEtWStWHtWStWHBWd-BWatCEStCEHWR1WR2CE1 Masks ADSPWR3CEtCEStCEHCE2 and CE3 only sampled with ADSP or ADSCUnselected with CE2CE2tCEStCEHCE2OEHigh-ZtDStDHDATAOUTDATAINHigh-Z1aBW4-BW1 only are applied to first cycle of WR22a2b2c2d3aSingle WriteBurst WriteWriteUnselectedIntegrated Silicon Solution, Inc. — 1-800-379-4774Rev.E

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SNOOZE MODE ELECTRICAL CHARACTERISTICS

SymbolISB2tPDStPUStZZItRZZI

Parameter

Current during SNOOZE MODEZZ active to input ignoredZZ inactive to input sampledZZ active to SNOOZE currentZZ inactive to exit SNOOZE current

ConditionsZZ ≥ Vih

Min.——2—0

Max.602—2—

ISSI

UnitmAcyclecyclecyclens

SNOOZE MODE TIMING

CLKtPDSZZ setup cycletPUSZZ recovery cycleZZtZZIIsupplyISB2tRZZIAll Inputs (except ZZ)Deselect or Read OnlyDeselect or Read OnlyNormaloperationcycleOutputs (Q)High-ZDon't Care20Integrated Silicon Solution, Inc. — 1-800-379-4774Rev.E04/21/06

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IS61LF25672A IS61LF51236A IS61LF102418AIS61VF25672A IS61VF51236A IS61VF102418A

IEEE 1149.1 SERIAL BOUNDARY SCAN (JTAG)The IS61LF/VF51236A and IS61LF/VF102418A have aserial boundary scan Test Access Port (TAP) in the PBGApackage only. This port operates in accordance with IEEEStandard 1149.1-1900, but does not include all functionsrequired for full 1149.1 compliance. These functions fromthe IEEE specification are excluded because they placeadded delay in the critical speed path of the SRAM. TheTAP controller operates in a manner that does not conflictwith the performance of other devices using 1149.1 fullycompliant TAPs. The TAP operates using JEDEC stan-dard 2.5V I/O logic levels.

ISSI

TEST ACCESS PORT (TAP) - TEST CLOCK

The test clock is only used with the TAP controller. Allinputs are captured on the rising edge of TCK and outputsare driven from the falling edge of TCK.

TEST MODE SELECT (TMS)

The TMS input is used to send commands to the TAPcontroller and is sampled on the rising edge of TCK. Thispin may be left disconnected if the TAP is not used. The pinis internally pulled up, resulting in a logic HIGH level.

TEST DATA-IN (TDI)

The TDI pin is used to serially input information to theregisters and can be connected to the input of any register.The register between TDI and TDO is chosen by theinstruction loaded into the TAP instruction register. Forinformation on instruction register loading, see the TAPController State Diagram. TDI is internally pulled up andcan be disconnected if the TAP is unused in an application.TDI is connected to the Most Significant Bit (MSB) on anyregister.

DISABLING THE JTAG FEATURE

The SRAM can operate without using the JTAG feature.To disable the TAP controller, TCK must be tied LOW(Vss) to prevent clocking of the device. TDI and TMS areinternally pulled up and may be disconnected. They mayalternately be connected to VDD through a pull-up resistor.TDO should be left disconnected. On power-up, the de-vice will start in a reset state which will not interfere with thedevice operation.

TAP CONTROLLER BLOCK DIAGRAM

0Bypass Register 2 1 0Instruction RegisterTDI Selection Circuitry 31 30 29 Selection CircuitryTDO. . . 2 1 0Identification Register x . . . . . 2 1 0Boundary Scan Register*TCKTMSTAP CONTROLLER21

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TEST DATA OUT (TDO)

The TDO output pin is used to serially clock data-out fromthe registers. The output is active depending on thecurrent state of the TAP state machine (see TAP ControllerState Diagram). The output changes on the falling edge ofTCK and TDO is connected to the Least Significant Bit(LSB) of any register.

ISSI

is set LOW (Vss) when the BYPASS instruction is ex-ecuted.

Boundary Scan Register

The boundary scan register is connected to all input andoutput pins on the SRAM. Several no connect (NC) pins arealso included in the scan register to reserve pins for higherdensity devices. The x36 configuration has a 75-bit-longregister and the x18 configuration also has a 75-bit-longregister. The boundary scan register is loaded with thecontents of the RAM Input and Output ring when the TAPcontroller is in the Capture-DR state and then placedbetween the TDI and TDO pins when the controller is movedto the Shift-DR state. The EXTEST, SAMPLE/PRELOADand SAMPLE-Z instructions can be used to capture thecontents of the Input and Output ring.

The Boundary Scan Order tables show the order in whichthe bits are connected. Each bit corresponds to one of thebumps on the SRAM package. The MSB of the register isconnected to TDI, and the LSB is connected to TDO.

PERFORMING A TAP RESET

A Reset is performed by forcing TMS HIGH (VDD) for fiverising edges of TCK. RESET may be performed while theSRAM is operating and does not affect its operation. Atpower-up, the TAP is internally reset to ensure that TDOcomes up in a high-Z state.

TAP REGISTERS

Registers are connected between the TDI and TDO pinsand allow data to be scanned into and out of the SRAM testcircuitry. Only one register can be selected at a timethrough the instruction registers. Data is serially loadedinto the TDI pin on the rising edge of TCK and output on theTDO pin on the falling edge of TCK.

Scan Register Sizes

Register NameInstructionBypassIDBoundary ScanBit Size(x18)313275Bit Size(x36)313275Bit Size(x72)3132TBDInstruction Register

Three-bit instructions can be serially loaded into the in-struction register. This register is loaded when it is placedbetween the TDI and TDO pins. (See TAP Controller BlockDiagram)At power-up, the instruction register is loadedwith the IDCODE instruction. It is also loaded with theIDCODE instruction if the controller is placed in a resetstate as previously described.

When the TAP controller is in the CaptureIR state, the twoleast significant bits are loaded with a binary “01” patternto allow for fault isolation of the board level serial test path.

Identification (ID) Register

The ID register is loaded with a vendor-specific, 32-bitcode during the Capture-DR state when the IDCODEcommand is loaded to the instruction register. The IDCODEis hardwired into the SRAM and can be shifted out whenthe TAP controller is in the Shift-DR state. The ID registerhas vendor code and other information described in theIdentification Register Definitions table.

Bypass Register

To save time when serially shifting data through registers,it is sometimes advantageous to skip certain states. Thebypass register is a single-bit register that can be placedbetween TDI and TDO pins. This allows data to be shiftedthrough the SRAM with minimal delay. The bypass register

IDENTIFICATION REGISTER DEFINITIONS

Instruction FieldRevision Number(31:28)Device Depth(27:23)Device Width(22:18)ISSI Device ID(17:12)ISSI JEDEC ID(11:1)ID Register Presence(0)22

DescriptionReserved for version number.Defines depth of SRAM. 512K or 1MDefines with of the SRAM. x36 or x18Reserved for future use.Allows unique identification of SRAM vendor.Indicate the presence of an ID register.256Kx72xxxx0011000101xxxxx000110101011512K x 36xxxx0011100100xxxxx11M x 18xxxx0100000011xxxxx10001101010100011010101Integrated Silicon Solution, Inc. — 1-800-379-4774Rev.E04/21/06

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TAP INSTRUCTION SET

Eight instructions are possible with the three-bit instructionregister and all combinations are listed in the InstructionCode table. Three instructions are listed as RESERVEDand should not be used and the other five instructions aredescribed below. The TAP controller used in this SRAM isnot fully compliant with the 1149.1 convention becausesome mandatory instructions are not fully implemented.The TAP controller cannot be used to load address, data orcontrol signals and cannot preload the Input or Outputbuffers. The SRAM does not implement the 1149.1 com-mands EXTEST or INTEST or the PRELOAD portion ofSAMPLE/PRELOAD; instead it performs a capture of theInputs and Output ring when these instructions are executed.Instructions are loaded into the TAP controller during theShift-IR state when the instruction register is placed be-tween TDI and TDO. During this state, instructions areshifted from the instruction register through the TDI andTDO pins. To execute an instruction once it is shifted in,the TAP controller must be moved into the Update-IRstate.

ISSI

SAMPLE/PRELOAD

SAMPLE/PRELOAD is a 1149.1 mandatory instruction.The PRELOAD portion of this instruction is not imple-mented, so the TAP controller is not fully 1149.1 compli-ant. When the SAMPLE/PRELOAD instruction is loadedto the instruction register and the TAP controller is in theCapture-DR state, a snapshot of data on the inputs andoutput pins is captured in the boundary scan register.It is important to realize that the TAP controller clockoperates at a frequency up to 10 MHz, while the SRAMclock runs more than an order of magnitude faster. Be-cause of the clock frequency differences, it is possible thatduring the Capture-DR state, an input or output will under-go a transition. The TAP may attempt a signal capturewhile in transition (metastable state). The device will notbe harmed, but there is no guarantee of the value that willbe captured or repeatable results.

To guarantee that the boundary scan register will capturethe correct signal value, the SRAM signal must be stabi-lized long enough to meet the TAP controller’s capture set-up plus hold times (tCS and tCH). To insure that the SRAMclock input is captured correctly, designs need a way tostop (or slow) the clock during a SAMPLE/PRELOADinstruction. If this is not an issue, it is possible to captureall other signals and simply ignore the value of the CLK andCLK captured in the boundary scan register.

Once the data is captured, it is possible to shift out the databy putting the TAP into the Shift-DR state. This places theboundary scan register between the TDI and TDO pins.Note that since the PRELOAD part of the command is notimplemented, putting the TAP into the Update to the Update-DRstate while performing a SAMPLE/PRELOAD instruction willhave the same effect as the Pause-DR command.

EXTEST

EXTEST is a mandatory 1149.1 instruction which is to beexecuted whenever the instruction register is loaded withall 0s. Because EXTEST is not implemented in the TAPcontroller, this device is not 1149.1 standard compliant.The TAP controller recognizes an all-0 instruction. Whenan EXTEST instruction is loaded into the instruction regis-ter, the SRAM responds as if a SAMPLE/PRELOADinstruction has been loaded. There is a difference betweenthe instructions, unlike the SAMPLE/PRELOAD instruction,EXTEST places the SRAM outputs in a High-Z state.

IDCODE

The IDCODE instruction causes a vendor-specific, 32-bitcode to be loaded into the instruction register. It alsoplaces the instruction register between the TDI and TDOpins and allows the IDCODE to be shifted out of the devicewhen the TAP controller enters the Shift-DR state. TheIDCODE instruction is loaded into the instruction registerupon power-up or whenever the TAP controller is given atest logic reset state.

BYPASS

When the BYPASS instruction is loaded in the instructionregister and the TAP is placed in a Shift-DR state, thebypass register is placed between the TDI and TDO pins.The advantage of the BYPASS instruction is that it short-ens the boundary scan path when multiple devices areconnected together on a board.

SAMPLE-Z

The SAMPLE-Z instruction causes the boundary scanregister to be connected between the TDI and TDO pinswhen the TAP controller is in a Shift-DR state. It alsoplaces all SRAM outputs into a High-Z state.

RESERVED

These instructions are not implemented but are reservedfor future use. Do not use these instructions.

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INSTRUCTION CODES

Code000

InstructionEXTEST

Description

ISSI

Captures the Input/Output ring contents. Places the boundary scan registerbetween the TDI and TDO. Forces all SRAM outputs to High-Z state. Thisinstruction is not 1149.1 compliant.

Loads the ID register with the vendor ID code and places the register between TDIand TDO. This operation does not affect SRAM operation.

Captures the Input/Output contents. Places the boundary scan register betweenTDI and TDO. Forces all SRAM output drivers to a High-Z state.Do Not Use: This instruction is reserved for future use.

Captures the Input/Output ring contents. Places the boundary scan register

between TDI and TDO. Does not affect the SRAM operation. This instruction does notimplement 1149.1 preload function and is therefore not 1149.1 compliant.Do Not Use: This instruction is reserved for future use.Do Not Use: This instruction is reserved for future use.

Places the bypass register between TDI and TDO. This operation does notaffect SRAM operation.

001010011100

IDCODESAMPLE-ZRESERVEDSAMPLE/PRELOAD101110111

RESERVEDRESERVEDBYPASS

TAP CONTROLLER STATE DIAGRAM

Test Logic Reset10Run Test/Idle011Select DR0Capture DR0Shift DR1Exit1 DR0011Select IR01Capture IR0Shift IR1Exit1 IR0Pause IR10Exit2 IR1011Pause DR0101Exit2 DR1Update DR001Update IR024Integrated Silicon Solution, Inc. — 1-800-379-4774Rev.E04/21/06

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IS61LF25672A IS61LF51236A IS61LF102418AIS61VF25672A IS61VF51236A IS61VF102418A

TAP Electrical Characteristics Over the Operating Range(1,2)

SymbolVOH1VOH2VOL1VOL2VIHVILIX

Parameter

Output HIGH VoltageOutput HIGH VoltageOutput LOW VoltageOutput LOW VoltageInput HIGH VoltageInput LOW VoltageInput Load Current

IOLT = 2mAVss ≤ V I ≤ VDDQTest ConditionsIOH = –2.0 mAIOH = –100 μAIOL = 2.0 mAIOL = 100 μA

Min.1.72.1——1.7–0.3–5

ISSI

Max.——0.70.2VDD +0.30.75

VVVVVVmA

Units

Notes:

1.All Voltage referenced to Ground.

2.Overshoot: VIH (AC) ≤ VDD +1.5V for t ≤ tTCYC/2,Undershoot: Vil (AC) ≤ 0.5V for t ≤ tTCYC/2,

Power-up: VIH < 2.6V and VDD < 2.4V and VDDQ < 1.4V for t < 200 ms.

TAP AC ELECTRICAL CHARACTERISTICS(1,2) (OVER OPERATING RANGE)

SymbolParametertTCYCfTFtTHtTLtTMSStTDIStCStTMSHtTDIHtCHtTDOVtTDOX

TCK Clock cycle timeTCK Clock frequencyTCK Clock HIGHTCK Clock LOW

TMS setup to TCK Clock RiseTDI setup to TCK Clock RiseCapture setup to TCK RiseTMS hold after TCK Clock RiseTDI Hold after Clock RiseCapture hold after Clock RiseTCK LOW to TDO validTCK LOW to TDO invalid

Min.100—4040101010101010—0

Max.—10————————20—

UnitnsMHznsnsnsnsnsnsnsnsnsns

Notes:

1. Both tCS and tCH refer to the set-up and hold time requirements of latching data from the boundary scan register.2. Test conditions are specified using the load in TAP AC test conditions. tR/tF = 1 ns.

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TAP AC TEST CONDITIONS

Input pulse levelsInput rise and fall timesInput timing reference levelsOutput reference levels

Test load termination supply voltage

0 to 2.5V/0 to 3.0V

1ns

1.25V/1.5V1.25V/1.5V1.25V/1.5V

ISSI

50Ω1.25V/1.5VTDOZ0 = 50Ω20 pFGND®

TAP Output Load Equivalent

TAP TIMING

1 2 3 4 5 6tTHTHtTLTHTCKtTHTLtMVTH tTHMXTMStDVTH tTHDXTDItTLOVTDOtTLOXDON'T CAREUNDEFINED26Integrated Silicon Solution, Inc. — 1-800-379-4774Rev.E04/21/06

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IS61LF25672A IS61LF51236A IS61LF102418AIS61VF25672A IS61VF51236A IS61VF102418A

ISSI

BumpID1A6A5B5A4A4B3B3A2A2B1B1C1D1E1F1G2D2E2F2G

Bit #616263646566676869707172737475

SignalNameDQdDQdDQdDQdDQdDQdDQdDQdDQdAAAAA1A0

1J1K1L1M2J2K2L2M1N3P3R4R4P6P6R

165 PBGA BOUNDARY SCAN ORDER (512K x 36)

SignalBump

Bit #NameID1234567891011121314151617181920

MODEAAAAAAAAAZZDQaDQaDQaDQaDQaDQaDQaDQaDQa

1R6N11P8P8R9R9P10P10R11R11H11N11M11L11K11J10M10L10K10J

Bit #2122232425262728293031323334353637383940

SignalBump

NameIDDQbDQbDQbDQbDQbDQbDQbDQbDQbNCAAADVADSPADSCOEBWEGWCLKNC

11G11F11E11D10G10F10E10D11C11A10A10B9A9B8A8B7A7B6B11B

Bit #4142434445464748495051525354555657585960

Signal

NameNCCE2BWaBWbBWcBWdCE2CEAANCDQcDQcDQcDQcDQcDQcDQcDQcDQc

BumpID

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IS61LF25672A IS61LF51236A IS61LF102418AIS61VF25672A IS61VF51236A IS61VF102418A

ISSI

BumpID1A6A5B5A4A4B3B3A2A2B1B1C1D1E1F1G2D2E2F2G

Bit #616263646566676869707172737475

SignalNameDQbDQbDQbDQbDQbNCNCNCNCAAAAA1A0

1J1K1L1M1N2K2L2M2J3P3R4R4P6P6R

165 PBGA BOUNDARY SCAN ORDER (1M x 18)

SignalBump

Bit #NameID1234567891011121314151617181920

MODEAAAAAAAAAZZNCNCNCNCNCDQaDQaDQaDQa

1R6N11P8P8R9R9P10P10R11R11H11N11M11L11K11J10M10L10K10J

Bit #2122232425262728293031323334353637383940

SignalBump

NameIDDQaDQaDQaDQaDQaNCNCNCNCAAAADVADSPADSCOEBWEGWCLKNC

11G11F11E11D11C10F10E10D10G11A10A10B9A9B8A8B7A7B6B11B

Bit #4142434445464748495051525354555657585960

Signal

NameNCCE2BWaNCBWbNCCE2CEAANCNCNCNCNCNCDQbDQbDQbDQb

BumpID

28Integrated Silicon Solution, Inc. — 1-800-379-4774Rev.E04/21/06

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IS61LF25672A IS61LF51236A IS61LF102418AIS61VF25672A IS61VF51236A IS61VF102418A

209 BOUNDARY SCAN ORDER (256K X 72)

ISSI

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IS61LF25672A IS61LF51236A IS61LF102418AIS61VF25672A IS61VF51236A IS61VF102418A

ORDERING INFORMATION (VDD = 3.3V/VDDQ = 2.5V/3.3V)Commercial Range: 0°C to +70°C

Configuration256Kx72512Kx36

Access Time

6.56.5

Order Part NumberIS61LF25672A-6.5B1IS61LF51236A-6.5TQIS61LF51236A-6.5B2IS61LF51236A-6.5B3

512Kx36

7.5

IS61LF51236A-7.5TQIS61LF51236A-7.5B2IS61LF51236A-7.5B3IS61LF102418A-6.5TQIS61LF102418A-6.5B2IS61LF102418A-6.5B3

1Mx18

7.5

IS61LF102418A-7.5TQIS61LF102418A-7.5B2IS61LF102418A-7.5B3

Package209 PBGA100 TQFP119 PBGA165 PBGA100 TQFP119 PBGA165 PBGA100 TQFP119 PBGA165 PBGA100 TQFP119 PBGA165 PBGA

ISSI

1Mx186.5

Industrial Range: -40°C to +85°C

Configuration256Kx72512Kx36

Access Time

6.56.5

Order Part NumberIS61LF25672A-6.5B1IIS61LF51236A-6.5TQIIS61LF51236A-6.5B2IIS61LF51236A-6.5B3IIS61LF51236A-7.5TQIIS61LF51236A-7.5TQLIIS61LF51236A-7.5B2IIS61LF51236A-7.5B3IIS61LF51236A-7.5B3LIIS61LF102418A-6.5TQIIS61LF102418A-6.5B2IIS61LF102418A-6.5B3I

1Mx18

7.5

IS61LF102418A-7.5TQIIS61LF102418A-7.5TQLIIS61LF102418A-7.5B2IIS61LF102418A-7.5B3I

Package209 PBGA100 TQFP119 PBGA165 PBGA

100 TQFP

100 TQFP, Lead-free119 PBGA165 PBGA

165 PBGA, Lead-free100 TQFP119 PBGA165 PBGA

100 TQFP

100 TQFP, Lead-free119 PBGA165 PBGA

512Kx367.5

1Mx186.5

30Integrated Silicon Solution, Inc. — 1-800-379-4774Rev.E04/21/06

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IS61LF25672A IS61LF51236A IS61LF102418AIS61VF25672A IS61VF51236A IS61VF102418A

ORDERING INFORMATION (VDD = 2.5V /VDDQ = 2.5V)Commercial Range: 0°C to +70°C

Configuration256Kx72512Kx36

Access Time

6.56.5

Order Part NumberIS61VF25672A-6.5B1IS61VF51236A-6.5TQIS61VF51236A-6.5B2IS61VF51236A-6.5B3

512Kx36

7.5

IS61VF51236A-7.5TQIS61VF51236A-7.5B2IS61VF51236A-7.5B3IS61VF102418A-6.5TQIS61VF102418A-6.5B2IS61VF102418A-6.5B3

1Mx18

7.5

IS61VF102418A-7.5TQIS61VF102418A-7.5B2IS61VF102418A-7.5B3

Package209 PBGA100 TQFP119 PBGA165 PBGA100 TQFP119 PBGA165 PBGA100 TQFP119 PBGA165 PBGA100 TQFP119 PBGA165 PBGA

ISSI

1Mx186.5

Industrial Range: -40°C to +85°C

Configuration256Kx72512Kx36

Access Time

6.56.5

Order Part NumberIS61VF25672A-6.5B1IIS61VF51236A-6.5TQIIS61VF51236A-6.5B2IIS61VF51236A-6.5B3IIS61VF51236A-7.5TQIIS61VF51236A-7.5TQLIIS61VF51236A-7.5B2IIS61VF51236A-7.5B3IIS61VF102418A-6.5TQIIS61VF102418A-6.5B2IIS61VF102418A-6.5B3I

1Mx18

7.5

IS61VF102418A-7.5TQIIS61VF102418A-7.5B2IIS61VF102418A-7.5B3I

Package209 PBGA100 TQFP119 PBGA165 PBGA

100 TQFP

100 TQFP, Lead-free119 PBGA165 PBGA100 TQFP119 PBGA165 PBGA100 TQFP119 PBGA165 PBGA

512Kx367.5

1Mx186.5

Integrated Silicon Solution, Inc. — 1-800-379-4774Rev.E04/21/06

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PACKAGING INFORMATION

Mini Ball Grid Array - 209 Ball BGA

Package Code: B (14 mm x 22mm Body, 1.0 mm Ball Pitch)

ISSI

φ b (209X) 11 10 9 8 7 6 5 4 3 2 1ABCDEFGHJKLMNPRTUVYe®

1 2 3 4 5 6 7 8 9 10 11ABCDEFGHJKLMNPRTUVYeDD1A3A1SEATING PLANEA2AE1EMILLIMETERSSym.N0.LeadsAA1A2A3DD1EE1eb— —0.65INCHESMin.Typ.Max.Notes:1. Controlling dimensions are in millimeters.Min.Typ.Max.209—0.540.701.95—0.75— — —0.0210.077 — 0.40 0.500.600.016 0.0200.0240.0260.0280.0300.8620.8660.8700.709 BSC0.5470.5510.5550.394 BSC0.039BSC0.0200.0240.02821.9022.0022.1018.00 BSC13.9014.0014.1010.00 BSC1.00BSC0.500.600.70Copyright © 2003 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any timewithout notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised toobtain the latest version of this device specification before relying on any published information and before placing orders for products.

Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774Rev.D08/22/03

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PACKAGING INFORMATION

Plastic Ball Grid Array

Package Code: B (119-pin)

ISSI

φ b (119X)7654321ABCDEFGHJKLMNPRTU®

EA30ϒDD2D1eA2E2A3A1E1A4SEATING PLANEMILLIMETERSSym.N0.LeadsAA1A2A3A4bDD1D2EE1E2e—0.500.801.300.6021.8019.4013.8011.90INCHESMin.Max.Notes:Min.119Max.2.410.701.001.700.9022.2019.6014.2012.10—0.0200.0320.0510.0240.8580.7640.5430.4690.0950.0280.0390.0670.0350.8740.7720.5590.4761. Controlling dimension: millimeters, unless otherwise specified.2. BSC = Basic lead spacing between centers.3. Dimensions D1 and E do not include mold flash protrusion and should be measured from the bottom of the package.4. Formed leads shall be planar with respect to one another within 0.004 inches at the seating plane.0.56 BSC0.022 BSC20.32 BSC0.800 BSC7.62 BSC1.27 BSC0.300 BSC0.050 BSCCopyright © 2003 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any timewithout notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised toobtain the latest version of this device specification before relying on any published information and before placing orders for products.

Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774Rev.B02/12/03

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PACKAGING INFORMATION

Ball Grid Array

Package Code: B (165-pin)

TOP VIEWA1 CORNER1 2 3 4 5 6 7 8 9 10 11A B C D E F G H J K L M N P Rφ b (165X)ISSI

BOTTOM VIEWA1 CORNER11 10 9 8 7 6 5 4 3 2 1A B C D E F G H J K L M N P R®

eDD1eE1EA2A1ABGA - 13mm x 15mmMILLIMETERSSym.N0.LeadsAA1A2DD1EE1eb— 0.25—14.9013.9012.909.90—0.40INCHESMin.Nom.Max.165Notes:1. Controlling dimensions are in millimeters.Min.Nom.Max. 165—0.330.7915.0014.0013.0010.001.200.40—15.1014.1013.1010.10—0.50——0.5870.5470.5080.390—0.016 —0.0310.5910.5510.5120.3940.0390.0180.047—0.5940.5550.5160.398—0.0200.010 0.0130.0161.000.45Copyright © 2003 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any timewithout notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised toobtain the latest version of this device specification before relying on any published information and before placing orders for products.

Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774Rev.A06/11/03

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PACKAGING INFORMATION

TQFP (Thin Quad Flat Pack Package)Package Code: TQISSI

DD1®

EE1N1CeSEATINGPLANEL1LA2A1bASymbolRef. Std.No. Leads (N)100A—1.60—0.063A10.050.150.0020.006A21.351.450.0530.057b0.220.380.0090.015D21.9022.100.8620.870D119.9020.100.7830.791E15.9016.100.6260.634E113.9014.100.5470.555e 0.65 BSC 0.026 BSCL0.450.750.0180.030L1 1.00 REF. 0.039 REF.C0o7o0o7oMillimetersMinMaxThin Quad Flat Pack (TQ)InchesMillimetersMinMaxMinMax128—1.600.050.151.351.450.170.2721.8022.2019.9020.1015.8016.2013.9014.10 0.50 BSC 0.450.75 1.00 REF.0o7oInchesMinMax—0.0630.0020.0060.0530.0570.0070.0110.8580.8740.7830.7910.6220.6380.5470.5550.020 BSC0.0180.0300.039 REF.0o7oNotes:1.All dimensioning andtolerancing conforms toANSI Y14.5M-1982.2.Dimensions D1 and E1 donot include mold protrusions.Allowable protrusion is 0.25mm per side. D1 and E1 doinclude mold mismatch andare determined at datumplane -H-.3.Controlling dimension:millimeters.Integrated Silicon Solution, Inc. — 1-800-379-4774PK13197LQ Rev. D 05/08/03

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