简易交通控制器
一、 设计要求
设计一个交通控制器，用LED显示灯来表示交通状态，并以七段数码管显示器显示当前状态剩余秒数，具体要求如下：
1、 主干道绿灯亮时，支干道红灯亮，反之依然，二者交替允许通过；主干道每次放行35s，支干道25s；每次由绿灯变为红灯过程中，黄灯亮作为过度，黄灯亮5s；
2、 能实现正常的倒计时显示功能；
3、 能实现总体清零功能，计数器由初始状态开始计数，对应状态的指示灯亮；
4、 能实现特殊状态的功能的显示，进入特殊状态时，东—西、南—北均显示红灯状态；
二、 设计原理图
三、 程序如下
module jiao_tong(clk,jin,ra,ya,ga,rb,yb,gb,seg7,scan);
input clk,jin;
output ra,ya,ga,rb,yb,gb;
output[7:0] scan;
output[7:0] seg7;
reg ra,ya,ga,rb,yb,gb;
reg[7:0] scan;
reg[7:0] seg7;
reg[1:0] state,next_state;
parameter state0=2'b00,state1=2'b01,state2=2'b10,state3=2'b11;
reg clk1khz,clk1hz;
reg[3:0] one,ten;
reg[1:0] cnt;
reg[3:0] data;
reg[7:0] seg7_temp;
reg r1,r2,g1,g2,y1,y2;
reg[14:0] count1;
reg[8:0] count2;
reg a;
reg[3:0] qh,ql;
initial scan<=8'b00000000;
always @(posedge clk)
begin
if(count1=='d25000)
begin clk1khz<=~clk1khz;count1<=0;end
else
begin count1<=count1+1'b1;end
end
always @(posedge clk1khz)
begin
if(count2=='d500)
begin clk1hz<=~clk1hz;count2<=0;end
else
begin count2<=count2+1'b1;end
end
always @(posedge clk1hz)
begin
state=next_state;
case(state)
state0:begin
if(jin)
begin
if(!a)
begin qh<='b0011;ql<='b0101;a<=1;
r1<=0;y1<=0;g1<=1; r2=1;y2<=0;g2<=0;
end
else
begin if(!qh&&!ql)
begin next_state<=state1;a<=0;
qh<='b0000;ql<='b0000;
end
else if(!ql)
begin ql<='b1001;qh<=qh-1'b1;
end
else
begin ql<=ql-1'b1;
end
end
end
end
state1:begin
if(jin)
begin
if(!a)
begin qh<='b0000;ql<='b0101;a<=1;
r1<=0;y1<=1;g1<=0; r2=1;y2<=0;g2<=0;
end
else
begin
if(!ql)
begin next_state<=state2;a<=0;
qh<='b0000;ql<='b0000;
end
else
begin ql<=ql-1'b1;
end
end
end
end
state2:begin
if(jin)
begin
if(!a)
begin qh<='b0010;ql<='b0101;a<=1;
r1<=1;y1<=0;g1<=0; r2=0;y2<=0;g2<=1;
end
else
begin if(!qh&&!ql)
begin next_state<=state3;a<=0;
qh<='b0000;ql<='b0000;
end
else if(!ql)
begin ql<='b1001;qh<=qh-1'b1;
end
else
begin ql<=ql-1'b1;
end
end
end
end
state3:begin
if(jin)
begin
if(!a)
begin qh<='b0000;ql<='b0101;a<=1;
r1<=1;y1<=0;g1<=0; r2=0;y2<=1;g2<=0;
end
else
begin
if(!ql)
begin next_state<=state0;a<=0;
qh<='b0000;ql<='b0000;
end
else
begin ql<=ql-1'b1;
end
end
end
end
endcase
one<=ql;ten<=qh;
end
//--------------------
always @(jin,clk1hz,r1,r2,g1,g2,y1,y2,seg7_temp)
begin
if(!jin)
begin ra<=r1||jin;rb<=r2||jin;
ga<=g1&&jin; gb<=g2&&jin;
ya<=y1&&jin; yb<=y2&&jin;
seg7[0]<=seg7_temp[0]||clk1hz;
seg7[1]<=seg7_temp[1]||clk1hz;
seg7[2]<=seg7_temp[2]||clk1hz;
seg7[3]<=seg7_temp[3]||clk1hz;
seg7[4]<=seg7_temp[4]||clk1hz;
seg7[5]<=seg7_temp[5]||clk1hz;
seg7[6]<=seg7_temp[6]||clk1hz;
seg7[7]<=seg7_temp[7]||clk1hz;
end
else
begin seg7[7:0]<=seg7_temp[7:0];
ra<=r1;rb<=r2;ga<=g1;gb<=g2;ya<=y1;yb<=y2;
end
end
//-----------------
always @(posedge clk1khz)
begin
if(cnt=='b01)
begin cnt<='b00;end
else begin cnt<=cnt+1'b1; end
end
always @(cnt,one,ten)
begin
case(cnt)
'b00 : begin data[3:0]<=ten;scan<='b01111111;end
'b01 : begin data[3:0]<=one;scan<='b10111111;end
default : begin data[3:0]<='bx;scan<='bx;end
endcase
end
always @(data)
begin
case(data[3:0])
4'b0000 : seg7_temp[7:0]<=8'b11000000;
4'b0001 : seg7_temp[7:0]<=8'b11111001;
4'b0010 : seg7_temp[7:0]<=8'b10100100;
4'b0011 : seg7_temp[7:0]<=8'b10110000;
4'b0100 : seg7_temp[7:0]<=8'b10011001;
4'b0101 : seg7_temp[7:0]<=8'b10010010;
4'b0110 : seg7_temp[7:0]<=8'b10000010;
4'b0111 : seg7_temp[7:0]<=8'b11111000;
4'b1000 : seg7_temp[7:0]<=8'b10000000;
4'b1001 : seg7_temp[7:0]<=8'b10010000;
default : seg7_temp[7:0]<=8'b10000110;
endcase
end
endmodule
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