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Preliminary Technical Data

High Performance ISM BandFSK/ASK Transceiver ICADF7020On-chip VCO and fractional-N PLL

On-chip 7-bit ADC and temperature sensor

±1 ppm RF output frequency accuracy possible from low cost 100 ppm crystal Digital RSSI

Leakage current <1 µA in power-down mode 48-lead ultrasmall MLF package (chip scale)

FEATURES

Low power, low IF transceiver Frequency bands:

433 MHz to 464 MHz 862 MHz to 928 MHz Data rates supported:

0.3 kbps to 200 kbps, FSK 0.3 kbps to 64 kbps, ASK 2.3 V to 3.6 V power supply Programmable output power:

−16 dBm to +13 dBm in 0.3 dBm steps Receiver sensitivity:

−117.5 dBm at 1 kbps, FSK −110.5 dBm at 9.6 kbps, FSK −106.5 dBm at 9.6 kbps, ASK Low power consumption: 19 mA in receive mode

22 mA in transmit mode (10 dBm output)

RSETVREG(1:4)ADCIN

APPLICATIONS

Low cost wireless data transfer Remote control/security systems Wireless metering Keyless entry Home automation

Process and building control Wireless voice

FUNCTIONAL BLOCK DIAGRAM

MUXOUTRLNABIASLDO(1:4)OFFSETCORRECTIONTEMPSENSORTESTMUXLNARFINRFINBIFFILTERGAINRSSIMUX7-BITADCFSK/ASKDEMODULATORDATASYNCHRONIZEROFFSETCORRECTIONAGCCONTROLFSKMODCONTROLGAUSSIANFILTERΣ-∆MODULATORCERxCLKTx/RxCONTROLTx/RxDATACLKOUTAFCCONTROLINT/LOCKPAOUTDIVIDERS/MUXINGDIVPN/N+1SLESDATAINSDATAOUTSCLK01975-PrG-001ASK/OOKMODCONTROLGAUSSIANFILTERSERIALPORTVCOCPPFDDIVRRINGOSCCLKDIVVCOINCPOUTOSCCLKOUT

Figure 1.

Rev. PrH

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ADF7020

Preliminary Technical DataDevice Programming after Initial Power-Up.........................22 Serial Interface................................................................................24 Readback Format........................................................................24 Register 0—N Register...............................................................25 Register 1—Oscillator/Filter Register......................................26 Register 2—Transmit Modulation Register (ASK/OOK

Mode)...........................................................................................27 Register 2—Transmit Modulation Register (FSK Mode).....28 Register 2—Transmit Modulation Register (GFSK/GOOK Mode)...........................................................................................29 Register 3—Receiver Clock Register.......................................30 Register 4—Demodulator Setup Register...............................31 Register 5—Sync Byte Register.................................................32 Register 6—Correlator/Demodulator Register......................33 Register 7—Readback Setup Register......................................34 Register 8—Power-Down Test Register..................................35 Register 9—AGC Register.........................................................36 Register 10—AGC 2 Register....................................................37 Register 11—AFC Register.......................................................37 Register 12—Test Register.........................................................38 Register 13—Offset Removal and Signal Gain Register.......39 Outline Dimensions.......................................................................40 Ordering Guide..........................................................................40

TABLE OF CONTENTS General Description.........................................................................3 Specifications.....................................................................................4 Timing Characteristics.....................................................................7 Absolute Maximum Ratings............................................................8 ESD Caution..................................................................................8 Pin Configuration and Function Descriptions.............................9 Frequency Synthesizer...................................................................11 Reference Input Section.............................................................11 Choosing Channels for Best System Performance.................13 Transmitter......................................................................................14 Modulation Schemes..................................................................14 Receiver Section..............................................................................16 RF Front End...............................................................................16 RSSI/AGC Section......................................................................17 FSK Demodulators on the ADF7020.......................................17 FSK Correlator/Demodulator...................................................17 Linear FSK Demodulator..........................................................19 AFC Section................................................................................19 Automatic Sync Word Recognition..........................................20 Applications Section.......................................................................21 LNA/PA Matching......................................................................21 Transmit Protocol and Coding Considerations.....................22 Image Rejection Calibration.....................................................22

REVISION HISTORY

Revision PrH: Preliminary Version

Rev. PrH | Page 2 of 40

Preliminary Technical Data

ADF7020A low IF architecture is used in the receiver (200 kHz),

minimizing power consumption and the external component count and avoiding interference problems at low frequencies. The ADF7020 supports a wide variety of programmable features including Rx linearity, sensitivity, and IF bandwidth, allowing the user to trade off receiver sensitivity and selectivity against current consumption, depending on the application. The receiver also features a patent-pending automatic frequency control (AFC) loop, allowing the PLL to track out the frequency error in the incoming signal.

An on-chip ADC provides readback of an integrated tempera-ture sensor, an external analog input, the battery voltage, or the RSSI signal, which provides savings on an ADC in some

applications. The temperature sensor is accurate to ±5°C over the full operating temperature range of −40°C to +85°C.

GENERAL DESCRIPTION

The ADF7020 is a low power, highly integrated FSK/GFSK/ ASK/OOK/GASK transceiver designed for operation in the license-free ISM bands at 433 MHz, 868 MHz, and 915 MHz. It is suitable for circuit applications that meet either the European ETSI-300-220 or the North American FCC (Part 15) regulatory standards. A complete transceiver can be built using a small number of external discrete components, making the ADF7020 very suitable for price-sensitive and area-sensitive applications. The transmit section contains a VCO and low noise

fractional-N PLL with output resolution of <1 ppm. The VCO operates at twice the fundamental frequency to reduce spurious emissions and frequency pulling problems.

The transmitter output power is programmable in 0.3 dB steps from −16 dBm to +13 dBm. The transceiver RF frequency, channel spacing, and modulation are programmable using a simple 3-wire interface. The device operates with a power

supply range of 2.3 V to 3.6 V and can be powered down when not in use.

Rev. PrH | Page 3 of 40

ADF7020

Preliminary Technical DataSPECIFICATIONS

VDD = 2.3 V to 3.6 V, GND = 0 V, TA = TMIN to TMAX, unless otherwise noted. Typical specifications are at VDD = 3 V, TA = 25°C.

All measurements are performed using the test circuit in Figure TBD using PN9 data sequence, unless otherwise noted. Table 1.

Parameter

RF CHARACTERISTICS Frequency Ranges

Frequency Ranges (Divide-by-2 Mode) Phase Frequency Detector Frequency TRANSMISSION PARAMETERS Data Rate FSK/GFSK Data Rate OOK/ASK Frequency Shift Keying

GFSK/FSK Frequency Deviation2, 3

Deviation Frequency Resolution Gaussian Filter BT

Adjacent Channel Power, GFSK

Max Unit Test Conditions 928 MHz 464 MHz 20 MHz

200 kbps 641kbps 110 kHz PFD = 3.625 MHz 620 kHz PFD = 20 MHz Hz PFD = 3.625 MHz dBc Channel spacing = 25 kHz, measured in

adjacent channel ± 8.5 kHz from center; DR = 4.8 kbps, FDEV = 2.4 kHz, FRF = 868 MHz

−50 dBc 868.95 MHz ± 250 kHz, DR = 38.4 kbps,

FDEV = 19.2 kHz

Amplitude Shift Keying ASK Modulation Depth 30 dB OOK –PA Off Feedthrough −50 dBm

Transmit Power −20 +13 dBm FRF = 915 MHz, VDD = 3.0 V, TA = 25°C TBD dBm FRF = 868 MHz, VDD = 3.0 V, TA = 25°C TBD dBm FRF = 433 MHz, VDD = 3.0 V, TA = 25°C Transmit Power Variation Highest Power Setting TBD dBm FRF = 915 MHz, VDD = 3.6 V 13 dBm FRF = 915 MHz, VDD = 3.0 V TBD dBm FRF = 915 MHz, VDD = 2.3 V Transmit Power Flatness TBD dB From 902 MHz to 928 MHz Programmable Step Size −20 dBm to +13 dBm 0.3125 dB Spurious Emissions during PLL Settling −57 dBm Mute PA until lock enabled (R2_DB5 =1 ) Integer Boundary −55 dBc 50 kHz loop BW Reference −65 dBc Harmonics Second Harmonic −27 −18 dBc Third Harmonic −21 −18 dBc All Other Harmonics −35 dBc VCO Frequency Pulling, OOK mod TBD kHz rms DR = 9.6 kbps

Optimum PA Load Impedance TBD Ω FRF = 915 MHz TBD Ω FRF = 868 MHz TBD Ω FRF = 433 MHz RECEIVER PARAMETERS FSK Input Sensitivity6 At BER = 1E − 3, FRF = 915 MHz High Sensitivity Mode −117.5 dBm DR = 1 kbps, FDEV = 5 kHz Low Current Mode −TBD dBm DR = 1 kbps, FDEV = 5 kHz See notes at end of table.

Rev. PrH | Page 4 of 40

Min Typ

862 433 RF/256

0.3 0.3 1 4.88 100 0.5 TBD

Preliminary Technical Data

ADF7020Min Typ −110.5 −104 −99 −TBD −TBD −TBD −106.5 −TBD 6.8 −3.2 −35

±50 1

Max Unit Test Conditions dBm DR = 9.6 kbps, FDEV = 10 kHz dBm DR = 9.6 kbps, FDEV = 10 kHz dBm DR = 200 kbps, FDEV = 50 kHz dBm DR = 200 kbps, FDEV = 50 kHz At BER = 1E − 3, FRF = 915 MHz dBm DR = 1 kbps dBm DR = 1 kbps dBm DR = 9.6 kbps dBm DR = 9.6 kbps dBm Pin = −20 dBm, 2 CW interferers dBm FRF = 915 MHz, f1 = FRF + 3 MHz dBm F2 = FRF + 6 MHz, maximum gain −57 dBm <1 GHz at antenna input −47 dBm >1 GHz at antenna input kHz IF_BW = 200 kHz TBD Bits TBD kHz

dB IF filter BW settings = 100 kHz, 150 kHz,

200 kHz

Desired signal 3 dB above the input 50 dB sensitivity level, CW interferer power level increased until BER = 10−3, image TBD dB channel excluded

30 TBD −3 TBD

dB dB dB dB

Parameter

High Sensitivity Mode Low Current Mode High Sensitivity Mode Low Current Mode OOK Input Sensitivity High Sensitivity Mode Low Current Mode High Sensitivity Mode Low Current Mode LNA and Mixer Input IP37

Enhanced Linearity Mode Low Current Mode High Sensitivity Mode Rx Spurious Emissions8

AFC Pull-In Range Response time Accuracy

Channel Filtering Adjacent Channel Rejection

(Offset = ±1 × IF Filter BW Setting) Second Adjacent Channel Rejection (Offset = ±2 × IF Filter BW Setting) Third Adjacent Channel Rejection (Offset = ±3 × IF Filter BW Setting) Image Channel Rejection

(Image Channel = FRF − 400 kHz) Co-channel Rejection

Wide-Band Interference Rejection

Uncalibrated Calibrated9

Swept from 100 MHz to 2 GHz, measured as channel rejection

Saturation (Maximum Input Level) 12 dBm FSK mode, BER = 10−3Input Impedance TBD Ω FRF = 915 MHz, RFIN, RFIN to GND TBD Ω FRF = 868 MHz TBD Ω FRF = 433 MHz RSSI Range at Input −100 to −36 dBm Linearity ±3 dB Absolute Accuracy TBD dB Response Time 350 µs Maximum input step change, AGC

included, RSSI ready for readback

PHASE LOCKED LOOP VCO Gain 65 MHz/V 902 MHz to 928 MHz band.,

VCO adjust = 0

130 MHz/V 860MHz to 870 MHz band,

VCO Adjust = 0

TBD MHz/V At 433MHz, VCO Adjust = 0 Phase Noise (In-Band) −92 dBc/Hz PA = 0 dBm, VDD = 3.0 V, PFD = 10 MHz,

FRF = 915 MHz, VCO BIAS = 4

Phase Noise (Out-of-Band) −110 dBc/Hz At 1 MHz offset Residual FM TBD Hz From 300 Hz to 5 kHz See notes at end of table.

Rev. PrH | Page 5 of 40

ADF7020

Preliminary Technical DataMin

Typ 40

Max

Unit µs

Test Conditions

Measured for a 10 MHz frequency step to within 5 ppm accuracy, PFD = 20 MHz, LBW = TBD

See the Reference Input Section

Parameter

PLL Settling Time

REFERENCE INPUT Crystal Reference External Oscillator Load capacitance Input Level

TIMING INFORMATION

Chip Enabled to Regulator Ready Crystal Oscillator Startup time Tx to Rx Turnaround Time LOGIC INPUTS

VINH, Input High Voltage VINL, Input Low Voltage IINH/IINL, Input Current CIN, Input Capacitance Control Clock Input LOGIC OUTPUTS

VOH,Output High Voltage VOL, Output Low Voltage CLKOUT Rise/Fall CLKOUT Load

TEMPERATURE RANGE—TA POWER SUPPLIES Voltage Supply AVDDDVDD

Transmit Current Consumption −20 dBm −10 dBm 0 dBm 10 dBm

Receive Current Consumption Low Current Mode High Sensitivity Mode Power-Down Mode

Low Power Sleep Mode

3.625 3.625

TBD 24 24

0.7 × V DD

DVDD − 0.4 0.4 V IOL = 500 µA 5 ns 10 pF −40 +85 °C 2.3 3.6 V AVDD AVDD FRF = 915 MHz, VDD = 3.0 V, PA is matched

in to 50 Ω

TBD mA 12 mA VCO_BIAS_SETTING = 3 15 mA 22 mA 19 TBD mA 21 TBD mA 0.1 1 µA

TBD CREG = 100 nF 1 With 19.2 MHz XTAL

350 µs + Time to synchronized data, includes AGC

(5 × TBIT) settling V 0.2 × V DDV ±1 µA 10 pF 50 MHz V IOH = 500 µA

MHz MHz pF CMOS levels µs ms

Higher data rates are achievable depending on local regulations.

For definition of frequency deviation, see the Register 2—Transmit Modulation Register (FSK Mode) section. 3

For definition of GFSK frequency deviation, see the Register 2—Transmit Modulation Register (GFSK/GOOK Mode) section. 4

Measured as maximum unmodulated power. Output power varies with both supply and temperature. 5

For matching details, see the LNA/PA Matching section. 6

See Table 5 for description of different receiver modes. 7

See Table 5 for description of different receiver modes. 8

Follow the matching and layout guidelines to achieve the relevant FCC/ETSI specifications. 9

See the Image Rejection Calibration section.

Rev. PrH | Page 6 of 40

Preliminary Technical Data

ADF7020TIMING CHARACTERISTICS

VDD = 3 V ± 10%; VGND = 0 V, TA = 25°C, unless otherwise noted. Guaranteed by design, but not production tested. Table 2.

Parameter t1 t2 t3 t4 t5 t6 t7t8t9t10

Limit at TMIN to TMAX<10 <10 <25 <25 <10 <20 Unit Test Conditions/Comments ns ns ns ns ns ns ns ns ns ns

SDATA to SCLK Setup Time SDATA to SCLK Hold Time SCLK High Duration SCLK Low Duration SCLK to SLE Setup Time SLE Pulse Width

SLE to SCLK Setup Time, Readback SCLK to SREAD Data Valid, Readback SREAD Hold Time after SCLK, Readback SCLK to SLE Disable Time, Readback

t3SCLKt4t1t2DB1(CONTROL BIT C2)DB0 (LSB)(CONTROL BIT C1)SDATADB31 (MSB)DB30DB2t601975-PrG-002SLEt5Figure 2. Serial Interface Timing Diagram

t1SCLKt2SDATAREG7 DB0(CONTROL BIT C1)SLEt3t10XRV16RV15RV2RV101975-PrG-003SREADt8t9Figure 3. Readback Timing Diagram

Rev. PrH | Page 7 of 40

ADF7020

Preliminary Technical Data

Stresses above those listed under Absolute Maximum Ratings

ABSOLUTE MAXIMUM RATINGS

TA = 25°C, unless otherwise noted. Table 3.

Parameter Rating may cause permanent damage to the device. This is a stress VDD to GND1−0.3 V to +5 V rating only and functional operation of the device at these or Analog I/O Voltage to GND −0.3 V to AVDD + 0.3 V any other conditions above those indicated in the operational Digital I/O Voltage to GND −0.3 V to DVDD + 0.3 V section of this specification is not implied. Exposure to absolute Operating Temperature Range maximum rating conditions for extended periods may affect Industrial (B Version) −40°C to +85°C device reliability. Storage Temperature Range −65°C to +125°C

This device is a high-performance RF integrated circuit with an Maximum Junction Temperature 125°C

ESD rating of <2 kV and it is ESD sensitive. Proper precautions TBD°C/W MLF θJA Thermal Impedance

should be taken for handling and assembly. Lead Temperature Soldering

Vapor Phase (60 s) 235°C

Infrared (15 s) 240°C

GND = CPGND = RFGND = DGND = AGND = 0 V.

ESD CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although this product features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality.

Rev. PrH | Page 8 of 40

Preliminary Technical Data

ADF7020VCO GNDPIN CONFIGURATION AND FUNCTION DESCRIPTIONS

484746454443424140393837VCOINVREG1VDD1RFOUTRFGNDRFINRFINBRLNAVDD4123456789PIN 1INDICATORMUXOUTCPOUTVREG3CVCOGND1OSC1OSC2VDD3GNDGNDVDD36353433CLKOUTDATA CLKDATA I/OINT/LOCKVDD2VREG2ADCINGND2SCLKSREADSDATASLEADF7020TOP VIEW(Not to Scale)3231302928272625RSET10VREG411GND412MIX_I13MIX_I14MIX_Q15MIX_Q16FILT_I17FILT_I18GND419FILT_Q20FILT_Q2122TEST_A23CE2401975-PrG-004GND4

Figure 4. Pin Configuration

Table 4. Pin Function Descriptions

Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13–18 19, 22 20, 21, 23 24 25 26 27 28

Mnemonic VCOIN VREG1 VDD1 RFOUT RFGND RFIN RFINB RLNA VDD4 RSET VREG4 GND4 MIX/FILT GND4

FILT/TEST_A CE SLE SDATA SREAD SCLK

Function

The tuning voltage on this pin determines the output frequency of the voltage controlled oscillator (VCO). The higher the tuning voltage, the higher the output frequency.

Regulator Voltage for PA Block. A 100 nF capacitor should be placed between this pin and ground for regulator stability and noise rejection.

Voltage Supply for PA Block. Decoupling capacitors (X7R or Tantalum) of 0.1 µF and 0.01 µF should be placed as close as possible to this pin.

The modulated signal is available at this pin. Output power levels are from −20 dBm to +13 dBm. The output should be impedance matched to the desired load using suitable components. See the Transmitter section. Ground for Output Stage of Transmitter.

LNA Input for Receiver Section. Input matching is required between the antenna and the differential LNA input to ensure maximum power transfer. See the LNA/PA Matching section. Complementary LNA Input. See the LNA/PA Matching section.

External bias resistor for LNA. Optimum resistor is 1.1 kΩ with 5% tolerance.

Voltage supply for LNA/MIXER block. This pin should be decoupled to ground with a 0.01 µF capacitor.

External Resistor to Set Charge Pump Current and Some Internal Bias Currents. Use 3.6 kΩ with 5% tolerance. Regulator Voltage for LNA/MIXER block. A 100 nF capacitor should be placed between this pin and GND for regulator stability and noise rejection. Ground for LNA/MIXER block.

Signal Chain Test Pins. These pins are high impedance under normal conditions and should be left unconnected.

Ground for LNA/MIXER block.

Signal Chain Test Pins. These pins are high impedance under normal conditions and should be left unconnected.

Chip Enable. Bringing CE low puts the ADF7020 into complete power-down. Register values are lost when CE is low, and the part must be reprogrammed once CE is brought high.

Load Enable, CMOS Input. When LE goes high, the data stored in the shift registers is loaded into one of the four latches. A latch is selected using the control bits.

Serial Data Input. The serial data is loaded MSB first with the two LSBs as the control bits. This pin is a high impedance CMOS input.

Serial Data Output. This pin is used to feed readback data from the ADF7020 to the microcontroller. The SCLK input is used to clock each readback bit (AFC, ADC readback) from the SREAD pin.

Serial Clock Input. This serial clock is used to clock in the serial data to the registers. The data is latched into the 24-bit shift register on the CLK rising edge. This pin is a digital CMOS input.

Rev. PrH | Page 9 of 40

ADF7020

Preliminary Technical DataPin No. 29 30

Function

Ground for Digital Section.

Analog-to-Digital Converter Input. The internal 7-bit ADC can be accessed through this pin. Full scale is 0 to 1.9 V. Readback is made using the SREAD pin.

31 VREG2 Regulator Voltage for Digital Block. A 100 nF capacitor should be placed between this pin and ground for

regulator stability and noise rejection.

32 VDD2 Voltage Supply for Digital Block. A decoupling capacitor (X7R or Tantalum) of 0.01 µF should be placed as

close as possible to this pin.

33 INT/LOCK Bidirectional Pin. In output mode (INTerrupt mode), the ADF7020 asserts the INT/ LOCK pin when it has found

a match for the preamble sequence.

In input mode (lock mode), the microcontroller can be used to lock the demodulator threshold when a valid preamble has been detected. Once the threshold is locked, NRZ data can be reliably received. In this mode, a demod lock can be asserted with minimum delay.

34 DATA I/O Transmit Data Input/Received Data Output. This is a digital pin and normal CMOS levels apply. 35 DATA CLK In receive mode, the pin outputs the synchronized data clock. The positive clock edge is matched to the

center of the received data. GIn GFSK transmit mode, the pin outputs an accurate clock to latch the data from the microcontroller into the transmit section at the exact required data rate. See the Gaussian Frequency Shift Keying (GFSK) section.

36 CLKOUT A Divided-Down Version of the Crystal Reference with Output Driver. The digital clock output can be used to

drive several other CMOS inputs such as a microcontroller clock. The output has a 50:50 mark-space ratio.

37 MUXOUT This pin provides the Lock_Detect signal, which is used to determine if the PLL is locked to the correct

frequency. Other signals include Regulator_Ready, which is an indicator of the status of the serial interface regulator.

38 OSC2 The reference crystal should be connected between this pin and OSC1. A TCXO reference can be used by

driving this pin with CMOS levels and disabling the crystal oscillator.

39 OSC1 The reference crystal should be connected between this pin and OSC2. 40 VDD3 Voltage Supply for the Charge Pump and PLL Dividers. This pin should be decoupled to ground with a

0.01 µF capacitor.

41 VRE3 Regulator Voltage for Charge Pump and PLL Dividers. A 100 nF capacitor should be placed between this pin

and ground for regulator stability and noise rejection.

42 CPOUT Charge Pump Output. This output generates current pulses that are integrated in the loop filter. The

integrated current changes the control voltage on the input to the VCO.

43 VDD Voltage Supply for VCO Tank Circuit. This pin should be decoupled to ground with a 0.01 µF capacitor. 44–47 GND Grounds for VCO Block. 48 CVCO A 22 nF capacitor should be placed between this pin and VREG1 to reduce VCO noise.

Mnemonic

GND2 ADCIN

Rev. PrH | Page 10 of 40

Preliminary Technical Data

ADF7020R Counter The 3-bit R counter divides the reference input frequency by an integer from 1 to 7. The divided-down signal is presented as the reference clock to the phase frequency detector (PFD). The divide ratio is set in Register 1. Maximizing the PFD frequency reduces the N value. This reduces the noise multiplied at a rate of 20 log(N) to the output, as well as reducing occurrences of spurious components. The R Register defaults to R = 1 on power-up: PFD [Hz] = XTAL/R MUXOUT and Lock Detect 01975-PrG-005FREQUENCY SYNTHESIZER

REFERENCE INPUT SECTION

The on-board crystal oscillator circuitry (Figure 5) can use an inexpensive quartz crystal as the PLL reference. The oscillator circuit is enabled by setting R1_DB12 high. It is enabled by default on power-up and is disabled by bringing CE low. Errors in the crystal can be corrected using the automatic frequency control (see the AFC Section) feature or by adjusting the

fractional-N value (see the N Counter section). A single-ended reference (TCXO, CXO) can also be used. The CMOS levels should be applied to OSC2 with R1_DB12 set low.

OSC1CP2OSC2CP1

The MUXOUT pin allows the user to access various digital points in the ADF7020. The state of MUXOUT is controlled by Bits R0_DB(29:31). Regulator Ready REGULATOR READY is the default setting on MUXOUT after the transceiver has been powered up. The power-up time of the regulator is typically 50 µs. Because the serial interface is powered from the regulator, the regulator must be at its nominal voltage before the ADF7020 can be programmed. The status of the regulator can be monitored at MUXOUT. When the REGULATOR READY signal on MUXOUT is high, programming of the ADF7020 can begin. DVDDFigure 5. Oscillator Circuit on the ADF7020

Two parallel resonant capacitors are required for oscillation at the correct frequency; their values are dependent on the crystal specification. They should be chosen so that the series value of capacitance added to the PCB track capacitance adds up to the load capacitance of the crystal, usually 20 pF. Track capacitance values vary from 2 pF to 5 pF, depending on board layout. Where possible, choose capacitors that have a very low

temperature coefficient to ensure stable frequency operation over all conditions. CLKOUT Divider and Buffer

The CLKOUT circuit takes the reference clock signal from the oscillator section, shown in Figure 5, and supplies a divided-down 50:50 mark-space signal to the CLKOUT pin. An even divide from 2 to 30 is available. This divide number is set in R1_DB(8:11). On power-up, the CLKOUT defaults to divide-by-8.

DVDDCLKOUTENABLE BITREGULATOR READYDIGITAL LOCK DETECTANALOG LOCK DETECTR COUNTER OUTPUTN COUNTER OUTPUTPLL TEST MODESΣ-∆ TEST MODES01975-PrG-007MUXCONTROLMUXOUTDGNDOSC1÷2CLKOUT01975-PrG-006DIVIDER1 TO 15 Figure 7. MUXOUT Circuit Figure 6. CLKOUT Stage Digital Lock Detect Digital lock detect is active high. The lock detect circuit is located at the PFD. When the phase error on five consecutive cycles is less than 15 ns, lock detect is set high. Lock detect remains high until 25 ns phase error is detected at the PFD. Because no external components are needed for digital lock detect, it is more widely used than analog lock detect. To disable CLKOUT, set the divide number to 0. The output buffer can drive up to a 20 pF load with a 10% rise time at 4.8 MHz. Faster edges can result in some spurious feedthrough to the output. A small series resistor (50 Ω) can be used to slow the clock edges to reduce these spurs at FCLK. Rev. PrH | Page 11 of 40

ADF7020

Preliminary Technical DataFor GFSK, it is recommended that an LBW of 2.0 to 2.5 times the data rate be used to ensure that sufficient samples are taken of the input data while filtering system noise. The free design tool ADIsimPLL can be used to design loop filters for the ADF7020.

Analog Lock Detect

This N-channel open-drain lock detect should be operated with an external pull-up resistor of 10 kΩ nominal. When a lock has been detected, this output is high with narrow low-going pulses. Voltage Regulators

The ADF7020 contains four regulators to supply stable voltages to the part. The nominal regulator voltage is 2.3 V. Each

regulator should have a 100 nF capacitor connected between VREG and GND. When CE is high, the regulators and other associated circuitry are powered on, drawing a total supply current of 2 mA. Bringing the chip-enable pin low disables the regulators, reduces the supply current to less than 1 µA, and erases all values held in the registers. The serial interface operates off a regulator supply; therefore, to write to the part, the user must have CE high and the regulator voltage must be stabilized. Regulator status (VREG4) can be monitored using the regulator ready signal from MUXOUT. Loop Filter

The loop filter integrates the current pulses from the charge pump to form a voltage that tunes the output of the VCO to the desired frequency. It also attenuates spurious levels generated by the PLL. A typical loop filter design is shown in Figure 8.

N Counter

The feedback divider in the ADF7020 PLL consists of an 8-bit integer counter and a 14-bit Σ-∆ fractional-N divider. The integer counter is the standard pulse-swallow type common in PLLs. This sets the minimum integer divide value to 31. The fractional divide value gives very fine resolution at the output, where the output frequency of the PLL is calculated as

FOUT =

REFERENCE IN4RPFD/CHARGEPUMPVCOFractional-NXTAL

× (Integer-N + ) R214

4NTHIRD-ORDERΣ-∆ MODULATORFRACTIONAL-NINTEGER-N01975-PrG-009

01975-PrG-008CHARGEPUMP OUTVCOFigure 9. Fractional-N PLL

Figure 8. Typical Loop Filter Configuration

The combination of the integer-N (maximum = 255) and the fractional-N (maximum = 16383/16384) give a maximum N divider of 255 + 1. Therefore, the minimum usable PFD is PDFMIN [Hz] = Maximum Required Output Frequency/(255 + 1) For example, when operating in the European 868 MHz to 870 MHz band, PFDMIN equals 3.4 MHz. Voltage Controlled Oscillator (VCO)

In FSK, the loop should be designed so that the loop bandwidth (LBW) is approximately five times the data rate. Widening the LBW excessively reduces the time spent jumping between frequencies, but can cause insufficient spurious attenuation. For ASK systems, a wider LBW is recommended. The sudden large transition between two power levels might result in VCO pulling and can cause a wider output spectrum than is desired. By widening the LBW to more than 10 times the data rate, the amount of VCO pulling is reduced, because the loop settles quickly back to the correct frequency. The wider LBW might restrict the output power and data rate of ASK-based systems compared with FSK-based systems.

Narrow-loop bandwidths can result in the loop taking long periods of time to attain lock. Careful design of the loop filter is critical to obtaining accurate FSK/GFSK modulation.

To minimize spurious emissions, the on-chip VCO operates from 1732 MHz to 1856 MHz. The VCO signal is then divided by 2 to give the required frequency for the transmitter and the required LO frequency for the receiver.

The VCO should be recentered, depending on the required frequency of operation, by programming the VCO adjust bits R1_DB(20:21).

The VCO is enabled as part of the PLL by the PLL-enable bit, R0_DB28.

A further frequency divide-by-2 is included to allow operation in the lower 433 MHz and 460 MHz bands. To enable operation in the these bands, R1_DB13 should be set to 1. The VCO needs an external 22 nF between the VCO and the regulator to reduce internal noise.

Rev. PrH | Page 12 of 40

Preliminary Technical Data

ADF7020CHOOSING CHANNELS FOR BEST SYSTEM PERFORMANCE

The fractional-N PLL allows the selection of any channel within 868 MHz to 928 MHz (and 433MHz using divide-by-2) to a resolution of <100 Hz. This also facilitates frequency hopping systems.

VCO Bias Current

VCO bias current can be adjusted using Bits R1_DB19 to R1_DB16. To ensure VCO oscillation, the minimum bias current setting under typical conditions is 2.5 mA. VCO BIASR1_DB (16:19)TO PA ANDN DIVIDERLOOP FILTERVCO÷2MUX÷2220µFCVCO PINVCO SELECT BITFigure 10. Voltage Controlled Oscillator (VCO)

Careful selection of the RF transmit channels must be made to achieve best spurious performance. The architecture of

fractional-N results in some level of the nearest integer channel 010-Grmoving through the loop to the RF output. These “beat-note” P-5791spurs are not attenuated by the loop, if the desired RF channel 0

and the nearest integer channel are separated by a frequency of less than the LBW.

The occurrence of beat-note spurs is rare, because the integer frequencies are at multiples of the reference, which is typically >10 MHz.

Beat-note spurs can be significantly reduced in amplitude by avoiding very small or very large values in the fractional register, using the frequency doubler. By having a channel 1 MHz away from an integer frequency, a 100 kHz loop filter can reduce the level to <−45 dBc. When using an external VCO, the fast lock (bleed) function reduces the spurs to <−60 dBc for the same conditions.

Rev. PrH | Page 13 of 40

ADF7020

Preliminary Technical DataThe PA is equipped with overvoltage protection, which makes it robust in severe mismatch conditions. Depending on the application, one can design a matching network for the PA to exhibit optimum efficiency at the desired radiated output power level for a wide range of different antennas, such as loop or monopole antennas. See the LNA/PA Matching section for details.

PA Bias Currents and Mute PA until Lock Bit

TRANSMITTER

RF OUTPUT STAGE

The PA of the ADF7020 is based on a single-ended, controlled current, open-drain amplifier that has been designed to deliver up to 13 dBm into a 50 Ω load at a maximum frequency of 928 MHz.

The PA output current and, consequently, the output power are programmable over a wide range. The PA configurations in FSK/GFSK and ASK/OOK modulation modes are shown in Figure 11 and Figure 12, respectively. In FSK/GFSK modulation mode, the output power is independent of the state of the

DATA_IO pin. In ASK/OOK modulation mode, it is dependent on the state of the DATA_IO pin and Bit R2_DB29, which selects the polarity of the TxData input. For each transmission mode, the output power can be adjusted as follows: • •

Control Bits R2_DB(30:31) facilitate an adjustment of the PA bias current to further extend the output power control range, if necessary. If this feature is not required, the default value of 7 µA is recommended. The output stage is powered down by resetting Bit R2_DB4. To reduce the level of undesired spurious emissions, the PA can be muted during the PLL lock phase by setting Bit R2_DB5 (mute PA until lock bit).

FSK/GFSK: The output power is set using bits R2_DB(9:14).

ASK: The output power for the inactive state of the TxData input is set by Bits R2_DB(15:20). The output power for the active state of the TxData input is set by Bits R2_DB(9:14). OOK: The output power for the active state of the TxData input is set by Bits R2_DB(9:14). The PA is muted when the TxData input is inactive.

R2_DB(30:31)26MODULATION SCHEMES

Frequency Shift Keying (FSK)

•

Frequency shift keying is implemented by setting the N value for the center frequency and then toggling this with the TxData line. The deviation from the center frequency is set using Bits R2_DB(15:23). The deviation from the center frequency in Hz is

FSKDEVIATION[Hz]=

PFD×ModulationNumber

214

IDACR2_DB(9:14)where Modulation Number is a number from 1 to 511 (R2_DB(15:23)) .

Select FSK using Bits R2_DB(6:8).

RFOUT+R2_DB4R2_DB501975-PrG-011RFGNDFROM VCODIGITALLOCK DETECT

4RFigure 11. PA Configuration in FSK/GFSK Mode

DATA I/OR2_DB29R2_DB(30:31)6IDAC66RFOUT+0R2_DB4R2_DB501975-PrG-012PFD/CHARGEPUMPPA STAGEVCOASK/OOK MODEFSK DEVIATIONFREQUENCY÷N–FDEV+FDEVTHIRD-ORDERΣ-∆ MODULATORR2_DB(9:14)R2_DB(15:23)TxDATAFRACTIONAL-NINTEGER-N01975-PrG-013

Figure 13. FSK Implementation

RFGNDFROM VCODIGITALLOCK DETECT

Figure 12. PA Configuration in ASK/OOK Mode

Rev. PrH | Page 14 of 40

Preliminary Technical Data

ADF7020Amplitude Shift Keying (ASK)

Amplitude shift keying is implemented by switching the output stage between two discrete power levels. This is accomplished by toggling the DAC, which controls the output level between two 6-bit values set up in Register 2. A zero TxData bit sends Bits R2_DB(15:20) to the DAC. A high TxData bit sends Bits R2_DB(9:14) to the DAC. A maximum modulation depth of 30 dB is possible.

Gaussian Frequency Shift Keying (GFSK)

Gaussian frequency shift keying reduces the bandwidth

occupied by the transmitted spectrum by digitally prefiltering the TxData. A TxCLK output line is provided from the ADF7020 for synchronization of TxData from the micro-controller. The TxCLK line can be connected to the clock input of a shift register that clocks data to the transmitter at the exact data rate.

Setting Up the ADF7020 for GFSK

To set up the frequency deviation, set the PFD and the mod control bits:

On-Off Keying (OOK)

On-off keying is implemented by switching the output stage to a certain power level for a high TxData bit and switching the output stage off for a zero. For OOK, the transmitted power for a high input is programmed using Bits R2_DB(9:14).

GFSKDEVIATION[Hz]=

PFD×2m

212Gaussian On-Off Keying (G-OOK)

Gaussian on-off keying represents a prefiltered form of OOK modulation. The usually sharp symbol transitions are replaced with smooth Gaussian filtered transitions, the result being a reduction in frequency pulling of the VCO. Frequency pulling of the VCO in OOK mode can lead to a wider than desired BW, especially if it is not possible to increase the loop filter BW > 300 kHz. The G-OOK sampling clock samples data at the data rate. (See the Setting Up the ADF7020 for GFSK section.)

where m is GFSK_MOD_CONTROL set using R2_DB(24:26). To set up the GFSK data rate:

DR[bps]=

PFD

DIVIDER_FACTOR×INDEX_COUNTER

For further information, see the application note, Using GFSK on the ADF7010, in the EVAL-ADF7010EB1 Technical Note.

Rev. PrH | Page 15 of 40

ADF7020

Preliminary Technical DataBased on the specific sensitivity and linearity requirements of the application, it is recommended to adjust control bits LNA_mode (R6_DB15) and mixer_linearity (R6_DB18) as outlined in Table 5.

The gain of the LNA is configured by the LNA_gain field, R9_DB(20:21), and can be set by either the user or the AGC logic.

RECEIVER SECTION

RF FRONT END

The ADF7020 is based on a fully integrated, low IF receiver architecture. The low IF architecture facilitates a very low

external component count and does not suffer from power-line-induced interference problems.

Figure 14 shows the structure of the receiver front end. The many programming options allow users to trade off sensitivity, linearity, and current consumption against each other in the way best suitable for their applications. To achieve a high level of resilience against spurious reception, the LNA features a differential input. Switch SW2 shorts the LNA input when transmit mode is selected (R0_DB27 = 0). This feature

facilitates the design of a combined LNA/PA matching network, avoiding the need for an external Rx/Tx switch. See the LNA/PA Matching section for details on the design of the matching network.

I (TO FILTER)RFINTx/Rx SELECT[R0_DB27]RFINBLNA MODE[R6_DB15]LNA CURRENT[R6_DB(16:17)]LNA GAIN[R9_DB(20:21)]LNA/MIXER ENABLE[R8_DB6]SW2LNALOQ (TO FILTER)MIXER LINEARITY[R6_DB18]IF Filter Settings/Calibration

Out-of-band interference is rejected by means of a fourth-order Butterworth polyphase IF filter centered around a frequency of 200 kHz. The bandwidth of the IF filter can be programmed between 100 kHz and 200 kHz by means of Control Bits

R1_DB(22:23), and should be chosen as a compromise between interference rejection, attenuation of the desired signal, and the AFC pull-in range.

To compensate for manufacturing tolerances, the IF filter should be calibrated once after power-up. The IF filter calibration logic requires that the IF filter divider in Bits

R6_DB(20:28) be set dependent on the crystal frequency. Once initiated by setting Bit R6_DB19, the calibration is performed automatically without any user intervention. The calibration time is 200 µs, during which the ADF7020 should not be accessed. It is important not to initiate the calibration cycle before the crystal oscillator has fully settled. If the AGC loop is disabled, the gain of IF filter can be set to three levels using the filter_gain field, R9_DB(20:21). The filter gain is adjusted automatically, if the AGC loop is enabled.

The signal in the image channel of the low IF mixer, located at a frequency of 400 kHz below the desired channel, is rejected due to the image rejection of the polyphase filter. The image

rejection performance of the IF filter is subject to manufactur-ing tolerances, and, to some extent, temperature drift. To improve the image rejection, a calibration procedure can be performed as outlined in the Image Rejection Calibration section.

01975-PrG-014

Figure 14. ADF7020 RF Front End

The LNA is followed by a quadrature downconversion mixer, which converts the RF signal to the IF frequency of 200 kHz. It is important to consider that the output frequency of the

synthesizer must be programmed to a value 200 kHz below the center frequency of the received channel.

The LNA has two basic operating modes: high gain/low noise mode and low gain/low power mode. To switch between these two modes, use the LNA_mode bit, R6_DB15. The mixer is also configurable between a low current and an enhanced linearity mode using the mixer_linearity bit, R6_DB18.

Table 5. LNA/Mixer Modes

Receiver Mode

High Sensitivity Mode (default)

RxMode2 1 10 0 −104 20 −15.9 Low Current Mode 1 3 0 −91 19 −3.2 Enhanced Linearity Mode 1 3 1 −101 19 6.8 RxMode5 1 10 1 TBD TBD −8.25 RxMode6 0 30 1 TBD TBD −28.8

Rev. PrH | Page 16 of 40

Sensitivity Rx Current

LNA Mode LNA Gain ValueMixer Linearity (DR = 9.6 kbps, Consumption

Input IP3 (dBm) (R6_DB15) R9_DB(21:20) (R6_DB18) fDEV = 10 kHz) (mA)

0 30 0 −110.5 22 −35

Preliminary Technical Data

ADF7020RSSI Formula (Converting to dBm)

Input_Power [dBm] = −110 dBm + (Readback_Code + Gain_Mode_Correction ) × 0.5 where:

Readback_Code is given by Bits RV7 to RV1 in the readback register (see Readback Format section).

Gain_Mode_Correction is given by the values in Table 6. LNA gain and filter gain (LG2/LG1, FG2/FG1) are also obtained from the readback register.

Table 6. Gain Mode Correction Table

LNA Gain (LG2, LG1) H (10) M (01) M (01) M (01) L (00)

RSSI/AGC SECTION

The RSSI is implemented as a successive compression log amp following the base-band channel filtering. The log amp achieves ±3 dB log linearity. It also doubles as a limiter to convert the signal-to-digital levels for the FSK demodulator. The RSSI itself is used for amplitude shift keying (ASK) demodulation. In ASK mode, extra digital filtering is performed on the RSSI value. Offset correction is achieved using a switched capacitor integra-tor in feedback around the log amp. This uses the BB offset clock divide. The RSSI level is converted for user readback and digitally controlled AGC by an 80-level (7-bit) flash ADC. This level can be converted to input power in dBm.

OFFSETCORRECTION1AAALATCHFSKDEMODIFWRIFWRIFWRIFWRCLKADCR01975-PrG-015RSSIASKDEMODFilter Gain (FG2, FG1) H (10) H (10) M (01) L (00) L (00)

Gain Mode Correction 0 11

19 + 11 = 30

19 + 19 + 11 = 49

19 + 19 + 19 + 11 = 68

Figure 15. RSSI Block Diagram

RSSI Thresholds

When the RSSI is above AGC_HIGH_THRESHOLD, the gain is reduced. When the RSSI is below AGC_LOW_THRESHOLD, the gain is increased. A delay (AGC_DELAY) is programmed to allow for settling of the loop. The user programs the two threshold values (recommended defaults, 27 and 76) and the delay (default, 10). The default AGC setup values should be adequate for most applications. The threshold values must be chosen to be more than 30 apart for the AGC to operate correctly.

An additional factor should be introduced to account for losses in the front-end matching network/antenna.

FSK DEMODULATORS ON THE ADF7020

The two FSK demodulators on the ADF7020 are • •

FSK correlator/demodulator Linear demodulator

Select these using the demod select bits, R4_DB(4:5).

FSK CORRELATOR/DEMODULATOR

The quadrature outputs of the IF filter are first limited and then fed to a pair of digital frequency correlators that perform band-pass filtering of the binary FSK frequencies at (IF + FDEV) and (IF − FDEV). Data is recovered by comparing the output levels from each of the two correlators. The performance of this frequency discriminator approximates that of a matched filter detector, which is known to provide optimum detection in the presence of AWGN.

FREQUENCY CORRELATORSLICEROffset Correction Clock

In Register 3, the user should set the BB offset clock divide bits R3_DB(4:5) to give an offset clock between 1 MHz and 2 MHz, where:

BBOS _CLK [Hz] = XTAL/(BBOS_CLK_DIVIDE) BBOS_CLK_DIVIDE can be set to 4, 8, or 16.

In Register 9, the user should select automatic gain control by selecting auto in R9_DB18 and auto in R9_DB19. The user should then program AGC low threshold R9_DB(4:10) and AGC high threshold R9_DB(11:17). The recommended/default values for the low and high thresholds are 30 and 70, respec-tively. In the AGC2 register the user should program the AGC delay to be long enough to allow the loop to settle. The recommended value is 10.

LIMITERSQIF– FDEVIF + FDEVPOSTDEMOD FILTERIDATASYNCHRONIZERAGC Information

IFRx DATARx CLK01975-PrG-0160DB(4:13)DB(14)DB(8:15)

Figure 16. FSK Correlator/Demodulator Block Diagram

Rev. PrH | Page 17 of 40

ADF7020

Preliminary Technical DataTo optimize the coefficients of the FSK correlator, two

additional bits, R6_DB14 and R6_DB29, must be assigned. The value of these bits depends on whether K (as defined above) is odd or even. These bits are assigned according to Table 7 and Table 8.

Table 7. When K Is Even

/2 R6_DB14 R6_DB29 Even Even 0 0 Even Odd 0 1

Postdemodulator Filter

A second-order, digital low-pass filter removes excess noise

from the demodulated bit stream at the output of the

discriminator. The bandwidth of this postdemodulator filter is programmable and must be optimized for the user’s data rate. If the bandwidth is set too narrow, performance is degraded due to intersymbol interference (ISI). If the bandwidth is set too wide, excess noise degrades the receiver’s performance. Typically, the 3 dB bandwidth of this filter is set at

approximately 0.75 times the user’s data rate, using Bits R4_DB(6:15).

Table 8. When K Is Odd

K (K + 1)/2 R6_DB14 Odd Even 1 Odd Odd 1 Bit Slicer

The received data is recovered by threshold detecting the output of the postdemodulator low-pass filter. In the correlator/ demodulator, the binary output signal levels of the frequency discriminator are always centered on zero. Therefore, the slicer threshold level can be fixed at zero and the demodulator

performance is independent of the run-length constraints of the transmit data bit stream. This results in robust data recovery, which does not suffer from the classic baseline wander

problems that exist in the more traditional FSK demodulators.

R6_DB29 0 1

Postdemodulator Bandwidth Register Settings

The 3 dB bandwidth of the postdemodulator filter is controlled by Bits R4_ DB(6:15) and is given by

Post_Demod_BWSetting=

210×2π×FCUTOFFDEMOD_CLK

Frequency errors are removed by an internal AFC loop that measures the average IF frequency at the limiter output and

where FCUTOFF is the target 3 dB bandwidth in Hz of the

applies a frequency correction value to the fractional-N

postdemodulator filter. This should typically be set to 0.75 times

synthesizer. This loop should be activated when the frequency

the data rate (DR).

errors are greater than approximately 40% of the transmit

KKfrequency deviation (see the AFC Section). Some sample settings for the FSK correlator/demodulator are

Data Synchronizer

An oversampled digital PLL is used to resynchronize the

received bit stream to a local clock. The oversampled clock rate of the PLL (CDR_CLK) must be set at 32 times the data rate. See the notes for the Register 3—Receiver Clock Register

section for a definition of how to program. The clock recovery PLL can accommodate frequency errors of up to ±2%.

DEMOD_CLK = 5 MHz DR = 9.6 kbps FDEV = 20 kHz Therefore,

FCUTOFF = 0.75 × 9.6 × 103 Hz

Post_Demod_BW = 211 π 7.2 × 103 Hz/(5 MHz) Post_Demod_BW = Round(9.26) = 9 and

K = Round(200 kHz)/20 kHz) = 10

Discriminator_BW = (5 MHz × 10)/(800 × 103) = 62.5 = 63 (rounded to nearest integer)

FSK Correlator Register Settings

To enable the FSK correlator/demodulator, Bits R4_DB(5:4) should be set to [01]. To achieve best performance, the bandwidth of the FSK correlator must be optimized for the specific deviation frequency that is used by the FSK transmitter. The discriminator BW is controlled in Register 6 by R6_DB(4:13) and is defined as

Table 9.

Setting Name Register Address Post_Demod_BW R4_DB(6:15) Discriminator BW R6_DB(4:13) Dot Product R6_DB14 Rx Data Invert R6_DB29

Value

0x09 0x3F 0 0

Discriminator_BW=(DEMOD_CLK×K)/(800×103) where:

DEMOD_CLK is as defined in the Register 3—Receiver Clock Register section, Note 2.

K = Round(200e3/FSK Deviation)

Rev. PrH | Page 18 of 40

Preliminary Technical Data

ADF7020The 3 dB bandwidth of this filter is typically set at approxi-mately 0.75 times the user data rate and is assigned by R4 _DB(6:15) as

Post_Demod_BW_Setting =

210×2π×FCUTOFFDEMOD_CLK

LINEAR FSK DEMODULATOR

A block diagram of the linear FSK demodulator is shown in Figure 17.

MUX 1ADC RSSI OUTPUTLEVELIF7Rx DATASLICERENVELOPEDETECTORLIMITERQFREQUENCYLINEAR DISCRIMINATORAVERAGINGFILTERIwhere FCUTOFF is the target 3 dB bandwidth in Hz of the postdemodulator filter.

AFC SECTION

01975-PrG-017FREQUENCYREADBACKANDAFC LOOPDB(6:15)

Figure 17. Block Diagram of Frequency Measurement System and

ASK.OOK/Linear FSK Demodulator

This method of frequency demodulation is useful when very short preamble length is required and the system protocol

cannot support the overhead of the settling time of the internal feedback AFC loop settling.

A digital frequency discriminator provides an output signal that is linearly proportional to the frequency of the limiter outputs. The discriminator output is then filtered and averaged using a combined averaging filter and envelope detector. The demodu-lated FSK data is recovered by threshold-detecting the output of the averaging filter, as shown in Figure 17. In this mode, the slicer output shown in Figure 17 is routed to the data synchro-nizer PLL for clock synchronization. To enable the linear FSK demodulator, set Bits R4_DB(4:5) to [00].

The 3 dB bandwidth of the postdemodulation filter is set in the same way as the FSK correlator/demodulator, which is set in R4_DB(6:15) and is defined as

The ADF7020 supports a real-time AFC loop, which is used to remove frequency errors that can arise due to mismatches between the transmit and receive crystals. This uses the

frequency discriminator block, as described in the Linear FSK Demodulator section (see Figure 17). The discriminator output is filtered and averaged to remove the FSK frequency

modulation using a combined averaging filter and envelope detector. In FSK mode, the output of the envelope detector provides an estimate of the average IF frequency.

Two methods of AFC, external and internal, are supported on the ADF7020 (in FSK mode only).

External AFC

The user reads back the frequency information through the ADF7020 serial port and applies a frequency correction value to the fractional-N synthesizer’s N divider.

The frequency information is obtained by reading the 16-bit signed AFC_readback, as described in the Readback Format section, and applying the following formula:

FREQ_RB [Hz] = (AFC_READBACK × DEMOD_CLK)/215

Note that while the AFC_READBACK value is a signed number, under normal operating conditions it is positive. In the absence of frequency errors, the FREQ_RB value is equal to the IF frequency of 200 kHz.

Post_Demod_BW_Setting=where:

210×2π×FCUTOFFDEMOD_CLK

Internal AFC

The ADF7020 supports a real-time internal automatic

frequency control loop. In this mode, an internal control loop automatically monitors the frequency error and adjusts the synthesizer N divider using an internal PI control loop. The internal AFC control loop parameters are controlled in Register 11. The internal AFC loop is activated by setting R11_DB20 to 1. A scaling coefficient must also be entered, based on the crystal frequency in use. This is set up in R11_DB(4:19) and should be calculated using

AFC_Scaling_Coefficient = (500 × 224)/XTAL Therefore, using a 10 MHz XTAL yields an AFC scaling coefficient of 839.

FCUTOFF is the target 3 dB bandwidth in Hz of the postdemodulator filter.

DEMOD_CLK is as defined in the Register 3—Receiver Clock Register section, Note 2.

ASK/OOK Operation

ASK/OOK demodulation is activated by setting Bits R4_DB(4:5) to [10].

Digital filtering and envelope detecting the digitized RSSI input via MUX 1, as shown in Figure 17, perform ASK/OOK demodulation. The bandwidth of the digital filter must be

optimized to remove any excess noise without causing ISI in the received ASK/OOK signal.

Rev. PrH | Page 19 of 40

ADF7020

Preliminary Technical DataThis feature can be used to alert the microprocessor that a valid channel has been detected. It relaxes the computational requirements of the microprocessor and reduces the overall power consumption. The INT/LOCK is automatically de-asserted again after nine data clock cycles.

The automatic sync/ID word detection feature is enabled by selecting demod mode 2 or 3 in the demodulator setup register. Do this by setting R4_DB(25:23) = [010] or [011]. Bits R5_DB(4:5) are used to set the length of the sync/ID word, which can be either 12, 16, 20, or 24 bits long. The transmitter must transmit the MSB of the sync byte first and the LSB last to ensure proper alignment in the receiver sync byte detection hardware.

For systems using FEC, an error tolerance parameter can also be programmed that accepts a valid match when up to three bits of the word are incorrect. The error tolerance value is assigned in R5_DB(6:7).

Maximum AFC Range

The maximum AFC frequency range is ±100 kHz. This is set by the maximum IF filter bandwidth of 200 kHz. Using the minimum IF filter bandwidth of 100 kHz, the AFC range is ±50 kHz.

When AFC errors have been removed using either the internal or external AFC, further improvement in the receiver’s sensi-tivity can be obtained by reducing the IF filter bandwidth using Bits R1_DB(22:23).

AUTOMATIC SYNC WORD RECOGNITION

The ADF7020 also supports automatic detection of the sync or ID fields. To activate this mode, the sync (or ID) word must be preprogrammed into the ADF7020. In receive mode, this preprogrammed word is compared to the received bit stream and, when a valid match is identified, the external pin INT/LOCK is asserted by the ADF7020.

Rev. PrH | Page 20 of 40

Preliminary Technical Data

ADF7020networks in a back-to-back configuration. Due to the

asymmetry of the network with respect to ground, a compro-mise between the input reflection coefficient and the maximum differential signal swing at the LNA input must be established. The use of appropriate CAD software is strongly recommended for this optimization.

Depending on the antenna configuration, the user might need a harmonic filter at the PA output to satisfy the spurious emission requirement of the applicable government regulations. The harmonic filter can be implemented in various ways, such as a discrete LC-filter. Dielectric low-pass filter components such as the LFL18924MTC1A052 (for operation in the 915 MHz band), or LFL18869MTC2A160 (for operation in the 868 MHz band), both by Murata Mfg. Co., Ltd., represent an attractive alternative to discrete designs. The immunity of the ADF7020 to strong out-of-band interference can be improved by adding a band-pass filter in the Rx path. Apart from discrete designs, SAW or dielectric filter components such as the

SAFCH869MAM0T00B0S, SAFCH915MAL0N00B0S,

DCFB2869MLEJAA-TT1, or DCFB3915MLDJAA-TT1, all by Murata Mfg. Co., Ltd., are well suited for this purpose.

APPLICATIONS SECTION

LNA/PA MATCHING

The ADF7020 exhibits optimum performance in terms of

sensitivity, transmit power, and current consumption only if its RF input and output ports are properly matched to the antenna impedance. For cost-sensitive applications, the ADF7020 is equipped with an internal Rx/Tx switch, which facilitates the use of a simple combined passive PA/LNA matching network. Alternatively, an external Rx/Tx switch such as the Analog Devices ADG919 can be used, which yields a slightly improved receiver sensitivity and lower transmitter power consumption.

External Rx/Tx Switch

Figure 18 shows a configuration using an external Rx/Tx switch. This configuration allows an independent optimization of the matching and filter network in the transmit and receive path, and is, therefore, more flexible and less difficult to design than the configuration using the internal Rx/Tx switch. The PA is biased through inductor L1, while C1 blocks dc current. Both elements, L1 and C1, also form the matching network, which transforms the source impedance into the optimum PA load impedance, ZOPT_PA.

VBATL1OPTIONALLPFANTENNACALAZOPT_PAZIN_RFINOPTIONALBPF(SAW)RFINLNARFINBPA_OUTPAInternal Rx/Tx Switch

Figure 19 shows the ADF7020 in a configuration where the internal Rx/Tx switch is used with a combined LNA/PA matching network. Depending on the application, the slight performance degradation caused by the internal Rx/Tx switch might be acceptable, allowing the user to take advantage of the cost-saving potential of this solution. The design of the combined matching network must compensate for the

reactance presented by the networks in the Tx and the Rx paths, taking the state of the Rx/Tx switch into consideration.

C1VBATL1PA_OUTPAANTENNAOPTIONALBPF OR LPFCALAZOPT_PAZIN_RFINRFINLNARFINBRx/Tx– SELECTCBZIN_RFINADF7020Figure 18. ADF7020 with External Rx/Tx Switch

Due to the differential LNA input, the LNA matching network must be designed to provide both a single-ended to differential conversion and a complex conjugate impedance match. The network with the lowest component count that can satisfy these requirements is the configuration shown in Figure 18, which consists of two capacitors and one inductor. A first-order implementation of the matching network can be obtained by understanding the arrangement as two L-type matching

CBZIN_RFINADF702001975-PrG-019ZOPT_PA depends on various factors such as the required output power, the frequency range, the supply voltage range, and the temperature range. Selecting an appropriate ZOPT_PA helps to minimize the Tx current consumption in the application. This datasheet contains a number of ZOPT_PA values for representa-tive conditions. Under certain conditions, however, it is

recommended to obtain a suitable ZOPT_PA value by means of a load-pull measurement.

01975-PrG-018ADG919

Figure 19. ADF7020 with Internal Rx/Tx Switch

The procedure typically requires several iterations until an acceptable compromise has been reached. The successful

implementation of a combined LNA/PA matching network for the ADF7020 is critically dependent on the availability of an

Rev. PrH | Page 21 of 40

ADF7020

Preliminary Technical DataIMAGE REJECTION CALIBRATION

The image channel in this receiver, with an IF at 200 kHz, is at −200 kHz or +400 kHz below the desired signal. The polyphase filter rejects this image with an asymmetric frequency response. The image rejection performance of the receiver is dependent on how well matched in amplitude the I and Q signals are, and how perfect the quadrature is between them, that is, how close to 90° apart they are. The uncalibrated image rejection perform-ance is approximately 30 dB. However, it is possible to improve on this performance by adjusting the I/Q phase/gain adjust bits in Register 10, resulting in an image rejection of approximately 45 dB.

Bits R10_DB(24:27) adjust the relative phase of the signal and Bits R10_DB(16:20) adjust the relative amplitude (see Figure 20).

LNAMIXERSPOLYPHASEFILTERaccurate electrical model for the PC board. In this context, the use of a suitable CAD package is strongly recommended. To avoid this effort, the reference design provided for the ADF7020 RF module can be used.

As with the external Rx/Tx switch, an additional LPF or BPF might be required to suppress harmonics in the transmit spectrum or to improve the resilience of the receiver against out-of-band interferers.

TRANSMIT PROTOCOL AND CODING CONSIDERATIONS

SYNCWORDIDFIELD01975-PrG-042PREAMBLEDATA FIELDCRC

Figure 20. Typical Format of a Transmit Protocol

A dc-free preamble pattern is recommended for FSK/ASK/ OOK demodulation. The recommended preamble pattern is a dc-free pattern such as a 10101010… pattern. Preamble patterns with longer run-length constraints such as 11001100…. can also be used. However, this results in a longer synchronization time of the received bit stream in the receiver.

Manchester coding can be used for the entire transmit protocol. However, the remaining fields that follow the preamble header do not have to use dc-free coding. For these fields, the ADF7020 can accommodate coding schemes with a run-length of up to 6 bits without any performance degradation.

If longer run-length coding must be supported, the ADF7020 has several other features that can be activated. These involve a range of programmable options that allow the envelope detector output to be frozen after preamble acquisition.

GAINLO ILO QPHASE01975-PrG-020

Figure 20. Phase/Gain Adjustment on ADF7020

DEVICE PROGRAMMING AFTER INITIAL POWER-UP

Basic mode is the minimum number of write sequences to power up the device. Enhanced mode uses the additional features of the ADF7020 to tailor the part to a particular application such as setting up a sync byte sequence or doing automatic frequency control.

The sample setting is for the following setup:

FRF = 915 MHz, FSK, DR = 9.868 kbps, ICP = 1.44 mA FDEV = 50 kHz, XTAL = 10 MHz, Correlator/Demodulator

Rev. PrH | Page 22 of 40

Preliminary Technical Data ADF7020

PRIMARYEXAMPLEPRIMARYEXAMPLEFUNCTIONSETTINGREGISTER WRITEFUNCTIONSETTINGPROGRAMPROGRAMFREQUENCY0x72DC 0000WRITE TO R0FREQUENCY0x0000SET UPSET UPOSCILLATOR0x86 9011WRITE TO R1OSCILLATOR0x0000AND IF FILTERAND IF FILTER12SET UP0-GrMODULATION0x8022 6012WRITE TO R3SET UP-P5Rx CLOCKS0x0000PARAMETERS7910

Figure 21. Basic Mode—Tx

WRITE TO R4SET UPDEMOD0x0000PRIMARYEXAMPLEFUNCTIONSETTINGSET UPWRITE TO R5SYNC BYTE0x0000PROGRAMFREQUENCY0x7ADB D710SEQUENCESET UPWRITE TO R6SET UPRx MODE0x0000OSCILLATOR0x86 9011AND IF FILTERSET UP AGCWRITE TO R9PARAMETERS AND0x0000SET UPLNA/GAIN FILTERRx CLOCKS0x64 2053SET UP I/QWRITE TO R10GAIN/PHASE0x0000SET UPADJUSTDEMOD0x0194320-G2r2SET UP AFCP0WRITE TO R11-SET UPGPARAMETERS0x0000-57r90x2C82 03261Rx MODE-P057

910

Figure 23. Enhanced Mode—Rx

Figure 22. Basic Mode—Rx

PRIMARYEXAMPLEREGISTER WRITEFUNCTIONSETTING420-GrWRITE TO R0CHANGE FREQUENCYAND CHANGE MODE0x0000P-5TO Rx7910

Figure 24. Change Mode from Tx to Rx

Rev. PrH | Page 23 of 40

ADF7020

Preliminary Technical DataRSSI Readback

SERIAL INTERFACE

The serial interface allows the user to program the eleven 32-bit registers using a 3-wire interface (SCLK, SDATA, and SLE). It consists of a level shifter, 32-bit shift register and eleven latches. Signals should be CMOS compatible. The serial interface is powered by the regulator, and, therefore, is inactive when CE is low.

Data is clocked into the register, MSB first, on the rising edge of each clock (SCLK). Data is transferred to one of eleven latches on the rising edge of SLE. The destination latch is determined by the value of the four control bits (C4 to C1). These are the bottom four LSBs, DB3 to DB0, as shown in the timing diagram in Figure 2. Data can also be read back on the SREAD pin.

The RSSI readback operation yields valid results in Rx mode with ASK or FSK signals. The format of the readback word is shown in Figure 25. It is comprised of the RSSI level informa-tion (Bits RV1 to RV7), the current filter gain (FG1, FG2), and the current LNA gain (LG1, LG2) setting. The filter and LNA gain are coded in accordance with the definitions in Register 9. With the reception of ASK modulated signals, averaging of the measured RSSI values improves accuracy. The input power can be calculated from the RSSI readback value as outlined in the RSSI/AGC Section.

Battery Voltage ADCIN/Temperature Sensor Readback

The battery voltage is measured at Pin VDD4. The readback information is contained in Bits RV1 to RV7. This also applies for the readback of the voltage at the ADCIN pin and the

temperature sensor. From the readback information, the battery or ADCIN voltage can be determined using

VBATTERY = (Battery_Voltage_Readback)/21.1 VADCIN = (ADCIN_Voltage_Readback)/42.1

READBACK FORMAT

The readback operation is initiated by writing a valid control word to the readback register and setting the readback-enable bit (R7_DB8 = 1). The readback can begin after the control word has been latched with the SLE signal. SLE must be kept high while the data is being read out. Each active edge at the SCLK pin clocks the readback word out successively at the SREAD pin, as shown in Figure 25, starting with the MSB first. The data appearing at the first clock cycle following the latch operation must be ignored.

Silicon Revision Readback

The silicon revision readback word is valid without setting any other registers, especially directly after power-up. The silicon revision word is coded with four quartets in BCD format. The product code (PC) is coded with two quartets extending from Bits RV9 to RV16. The revision code (RV) is coded with two quartets extending from Bits RV1 to RV8. The product code should read back as PC = #20h. The current revision code should read as RC = #30h.

AFC Readback

The AFC readback is valid only during the reception of FSK signals with either the linear or correlator demodulator active. The AFC readback value is formatted as a signed 16-bit integer comprised of Bits RV1 to RV16, and is scaled according to the following formula:

FREQ_RB [Hz] = (AFC_READBACK × DEMOD_CLK)/215

In the absence of frequency errors, the FREQ_RB value is equal to the IF frequency of 200 kHz. Note that, for the AFC readback to yield a valid result, the down-converted input signal must not fall outside the bandwidth of the analogue IF filter. At low-input signal levels, the variation in the readback value can be improved by averaging.

Filter Calibration Readback

The filter calibration readback word is contained in Bits RV1 to RV8, and is for diagnostic purposes only. Using the automatic filter calibration function, accessible through Register 6, is recommended.

READBACK MODEDB15AFC READBACKRSSI READBACKBATTERY VOLTAGE/ADCIN/TEMP. SENSOR READBACKSILICON REVISIONFILTER CAL READBACKRV16XDB14RV15XDB13RV14XDB12RV13XDB11RV12XDB10RV11LG2READBACK VALUEDB9RV10LG1DB8RV9FG2DB7RV8FG1DB6RV7RV7DB5RV6RV6DB4RV5RV5DB3RV4RV4DB2RV3RV3DB1RV2RV2DB0RV1RV1XRV160XRV150XRV140XRV130XRV120XRV110XRV100XRV90XRV8RV8RV7RV7RV7RV6RV6RV6RV5RV5RV5RV4RV4RV4RV3RV3RV3RV2RV2RV2RV1RV1RV101975-PrG-025Figure 25. Readback Value Table

Rev. PrH | Page 24 of 40

Preliminary Technical Data

ADF7020REGISTER 0—N REGISTER

PLLENABLETx/RxMUXOUT8-BIT INTEGER-N15-BIT FRACTIONAL-NADDRESSBITSDB31DB30DB29PLE1DB28DB27DB26DB25DB24DB23DB22DB21DB20DB19DB18DB17DB16DB15DB14DB13DB12DB11DB10DB9DB8DB7DB6DB5DB4C4 (0)DB3C3 (0)DB2C2 (0)DB1TR10101M300001111M200110011M101010101TRANSMIT/RECEIVETRANSMITRECEIVEM15000...1111M14000...1111M13000...1111.................................M3111...1111M2001...0011M1010...0101FRACTIONALDIVIDE RATIO456...32764327653276632767PLE1PLL ENABLEPLL OFFPLL ONMUXOUTREGULATOR READY (DEFAULT)R DIVIDER OUTPUTN DIVIDER OUTPUTDIGITAL LOCK DETECTANALOG LOCK DETECTTHREE-STATEPLL TEST MODESΣ-∆ TEST MODESN800...111N700...111N601...111N510...111N410...111N310...111N210...011N110...101N COUNTERDIVIDE RATIO3132...25325425501975-PrG-026C1 (0)DB0M15M14M13M12M11M10TR1M3M2M1M9M8M7M6M5M4M3M2M1N8N7N6N5N4N3N2N1

Figure 26.

Notes: 1. 2.

The Tx/Rx bit (R0_DB27) configures the part in Tx or Rx mode and also controls the state of the internal Tx/Rx switch.

FOUT=

Fractional-NXTAL

×(Integer-N+). R215Rev. PrH | Page 25 of 40

ADF7020

Preliminary Technical DataIF FILTER BWVCO BANDREGISTER 1—OSCILLATOR/FILTER REGISTER

CPCURRENTVCO BIASCLOCKOUTDIVIDEXTALDOUBLERVCOADJUSTXOSCENABLER COUNTERADDRESSBITSDB31DB30DB29DB28DB27DB26DB25DB24DB23DB22DB21DB20DB19DB18DB17DB16DB15DB14DB13DB12DB11DB10DB9DB8DB7DB6DB5DB4C4 (0)DB3C3 (0)DB2C2 (0)DB1VA20011VA10101FREQUENCYOF OPERATION880–950870–940860–930850–920X1XTAL OSC0OFF1ONV1VCO BIASCURRENT0.5mA1mA8mA01VCO BandMHz866–940433–470R300...1R201...1R110...1RF R COUNTERDIVIDE RATIO12...7VB400.1VB300.1VB201.1VB110.1D101XTALDOUBLERDISABLEENABLEDCLKOUTDIVIDE RATIOOFF24...30IR2IR100110101FILTERBANDWIDTH100kHz150kHz200kHzNOT USEDCP20011ICP(MA)CP1RSET3.6kΩ01010.30.91.52.101975-PrG-027CL4000...1CL3000...1CL2001...1CL1010...1C1 (1)DB0VA2VA1DD2DD1VB4VB3VB2VB1CL4CL3CL2CL1IR2IR1D1R3R2R1V1X1

Figure 27.

Notes: 1. 2.

Set the VCO adjust bits (R1_DB(20:21) to 0 for normal operation.

FOUT=

Fractional-NXTAL

×(Integer-N+). R215Rev. PrH | Page 26 of 40

Preliminary Technical Data

ADF7020MUTE PAUNTIL LOCKPAENABLEREGISTER 2—TRANSMIT MODULATION REGISTER (ASK/OOK MODE)

INDEXCOUNTERTxDATA INVERTPA BIASGFSK MODCONTROLMODULATION PARAMETERPOWER AMPLIFIERMODULATIONSCHEMEADDRESSBITSDB31DB30DB29DB28DB27DB26DB25DB24DB23DB22DB21DB20DB19DB18DB17DB16DB15DB14DB13DB12DB11DB10DB9DB8DB7DB6DB5DB4C4 (0)DB3C3 (0)DB2C2 (1)DB1PE1IC2IC1MC3MC2MC1XXXXX01POWER AMPLIFIEROFFONDI101TxDATATxDATAMUTE PA UNTILMP1LOCK DETECT HIGH01OFFONPA20101PA10011PA BIAS5µA7µA9µA11µAS300101S200011S101011MODULATION SCHEMEFSKGFSKASKOOKG - OOKPOWER AMPLIFIER OUTPUT LOW LEVELD6.D5D2D1X0000..1XX00...1.......1XX001..1XX010..1OOK MODEPA OFF–16.0dBm–16 + 0.45dBm–16 + 0.90dBm..13dBmPOWER AMPLIFIER OUTPUT HIGH LEVELP6..P2P10000..1......1......1X001..1X010..1PA OFF–16.0dBm–16 + 0.45dBm–16 + 0.90dBm..13dBmC1 (0)DB001975-PrG-028MC3MC2MC1MP1PA2PA1PE1DI1IC2IC1D9D8D7D6D5D4D3D2D1P6P5P4P3P2P1S3S2S1

Figure 28.

Note:

1. See the Transmitter section for a description of how the PA bias affects power amplifier level. Default level is 9 µA.

Rev. PrH | Page 27 of 40

ADF7020

Preliminary Technical DataMUTE PAUNTIL LOCKPAENABLEINDEXCOUNTERREGISTER 2—TRANSMIT MODULATION REGISTER (FSK MODE)

TxDATA INVERTPA BIASGFSK MODCONTROLMODULATION PARAMETERPOWER AMPLIFIERMODULATIONSCHEMEADDRESSBITSDB31DB30DB29DB28DB27DB26DB25DB24DB23DB22DB21DB20DB19DB18DB17DB16DB15DB14DB13DB12DB11DB10DB9DB8DB7DB6DB5DB44 (0)DB33 (0)DB22 (1)DB11 (0)DB0MC2MC3MC1MP1PA2PA1PE1DI1IC2IC1D9D8D7D6D5D4D3D2D1P6P5P4P3P2P1S3S2S1IC2IC1MC3MC2MC1XXXXXDI10TxDATA1TxDATAPA2PA1PA BIAS005µA017µA109µA1111µANotes:

FSTEP=PFD/214

PA Bias default = 9 µA.

FOR FSK MODE,D9....D3D2D1F DEVIATION0....000PLL MODE0....0011× F0....0102× FSTEP0....0113× FSTEP.........STEP1....111511× FSTEPFigure 29.

Rev. PrH | Page 28 of 40

CCCCPE1POWER AMPLIFIER0OFF1ONMUTE PA UNTILMP1LOCK DETECT HIGH0OFF1ONS3S2S1MODULATION SCHEME000FSK001GFSK010ASK011OOK111G - OOKPOWER AMPLIFIER OUTPUT LEVELP6..P2P10..XXPA OFF0..00–16.0dBm0..01–16 + 0.45dBm0..10–16 + 0.90dBm92......0-Gr......-P51111113dBm7910

Preliminary Technical Data

ADF7020MUTE PAUNTIL LOCKPAENABLEREGISTER 2—TRANSMIT MODULATION REGISTER (GFSK/GOOK MODE)

INDEXCOUNTERTxDATA INVERTPA BIASGFSK MODCONTROLMODULATION PARAMETERPOWER AMPLIFIERMODULATIONSCHEMEADDRESSBITSDB31DB30DB29DB28DB27DB26DB25DB24DB23DB22DB21DB20DB19DB18DB17DB16DB15DB14DB13DB12DB11DB10DB9DB8DB7DB6DB5DB4C4 (0)DB3C3 (0)DB2C2 (1)DB1D70000.1TxDATATxDATA.....................D30000.1D20011.1D10101.1DIVIDER_FACTORINVALID123.127PE101POWER AMPLIFIEROFFONDI101MUTE PA UNTILMP1LOCK DETECT HIGH01OFFONPA20101PA10011PA BIAS5µA7µA9µA11µAD90011INDEX_COUNTER163264128D80101GAUSSIAN– OOKMODEBLEED/BUFFER OFFOUTPUT BUFFER ONBLEED CURRENT ONBLEED/BUFFER ONS300101S200011S101011MODULATION SCHEMEFSKGFSKASKOOKG - OOKIC20011IC10101POWER AMPLIFIER OUTPUT LEVELP1P2..P60000..1......1......1X001..1X010..1PA OFF–16.0dBm–16 + 0.45dBm–16 + 0.90dBm..13dBmMC3MC2MC1GFSK_MOD_CONTROL00.100.101.101.7C1 (0)DB001975-PrG-030MC2MC3MC1MP1PA2PA1PE1DI1IC2IC1D9D8D7D6D5D4D3D2D1P6P5P4P3P2P1S3S2S1 Figure 30.

Notes: 1. 2. 3.

GFSK_DEVIATION = (2GFSK_MOD_CONTROL × PFD)/212. DR = PFD/(INDEX_COUNTER × DIVIDER_FACTOR). PA Bias default = 9 µA.

Rev. PrH | Page 29 of 40

ADF7020

Preliminary Technical DataDEMODCLOCK DIVIDEBB OFFSETCLOCK DIVIDEREGISTER 3—RECEIVER CLOCK REGISTER

ADDRESSBITSSEQUENCER CLOCK DIVIDECDR CLOCK DIVIDEDB31DB30DB29DB28DB27DB26DB25DB24DB23DB22DB21DB20DB19DB18DB17DB16DB15DB14DB13DB12DB11DB10DB9DB8DB7DB6DB5DB4DB3DB2DB1C2(1)C4(0)C3(0)SK800.11SK700.11..................SK300.11SK201.11SK110.01SEQ_CLK_DIVIDE12.254255BK2001OK20011OK10101BK101xBBOS_CLK_DIVIDE4816DEMOD_CLK_DIVIDE4123FS800.11FS700.11..................FS300.11FS201.11FS110.01CDR_CLK_DIVIDE01975-PrG-03112.254255C1(1)OK2OK1BK2BK1SK8SK7SK6SK5SK4SK3SK2SK1FS8FS7FS6FS5FS4FS3FS2FS1IR2IR1DB0

Figure 31.

Notes: 1.

Baseband offset clock frequency (BBOS_CLK) must be greater than 1 MHz and less than 2 MHz, where:

BBOS_CLK=

XTAL

BBOS_CLK_DIVIDE

2. The demodulator clock (DEMOD_CLK) must be < 12 MHz for FSK and < 6 MHz for ASK, where:

DEMOD_CLK=

XTAL

DEMOD_CLK_DIVIDE

3. Data/clock recovery frequency (CDR_CLK) should be within 2% of (32 × data rate), where:

CDR_CLK=

DEMOD_CLK

CDR_CLK_DIVIDE

Note that this might affect your choice of XTAL, depending on the desired data rate. 4.

The sequencer clock (SEQ_CLK) supplies the clock to the digital receive block. It should be close to 100 kHz for FSK and close to 40 kHz for ASK:

SEQ_CLK=

XTAL

SEQ_CLK_DIVIDE

Rev. PrH | Page 30 of 40

Preliminary Technical Data

ADF7020REGISTER 4—DEMODULATOR SETUP REGISTER

DEMOD LOCK/SYNC WORD MATCHDB24DEMODSELECTDEMODULATOR LOCK SETTINGPOSTDEMODULATOR BWADDRESSBITSDB31DB30DB29DB28DB27DB26DB25DB23DB22DB21DB20DB19DB18DB17DB16DW10DB15DW9DB14DW8DB13DW7DB12DB11DW5DB10DB9DB8DB7DB6DB5DB4DB3DB2DB1C2(0)C4(0)C3(1)DS20011DEMOD MODELM2LM1DL80123450000110011010101XDL8DEMOD LOCK/SYNC WORD MATCHSERIAL PORT CONTROL– FREE RUNNINGSERIAL PORT CONTROL– LOCK THRESHOLDSYNC WORD DETECT– FREE RUNNINGSYNC WORD DETECT– LOCK THRESHOLDINTERRUPT/LOCK PIN LOCKS THRESHOLDDEMOD LOCKED AFTER DL8–DL1 BITSINT/LOCK PIN––OUTPUTOUTPUTINPUT–DS10101DEMODULATORTYPELINEAR DEMODULATORCORRELATOR/DEMODULATORASK/OOKINVALIDMODE5 ONLYDL8000.11DL7000.11.....................DL3000.11DL2001.11DL1010.01LOCK_THRESHOLD_TIMEOUT012.254255C1(0)01975-PrG-032DW2DW6DW4DW3DW1LM2LM1DS2DS1DL6DL5DL4DL3DL2DL8DL7DL1DB0

Figure 32.

Notes : 1. 2. 3. 4.

The cutoff frequency of the postdemodulator filter should typically be 0.75 times the data rate.

Demodulator modes 1, 3, 4, and 5 are modes that can be activated to allow the ADF7020 to demodulate data-encoding schemes that have run-length constraints greater than 7.

Post_Demod_BW = 211 π FCUTOFF/DEMOD_CLK.

For Mode 5, the timeout delay to lock threshold = (LOCK_THRESHOLD_SETTING)/SEQ_CLK, where SEQ_CLK is defined in the Register 3—Receiver Clock Register section.

Rev. PrH | Page 31 of 40

ADF7020

Preliminary Technical DataMATCHINGTOLERANCESYNC BYTELENGTHREGISTER 5—SYNC BYTE REGISTER

SYNC BYTE SEQUENCECONTROLBITSDB31DB30DB29DB28DB27DB26DB25DB24DB23DB22DB21DB20DB19DB18DB17DB16DB15DB14DB13DB12DB11DB10DB9DB8DB7DB6DB5DB4DB3DB2DB1C2(0)C4(0)C3(1)PL20011PL10101SYNC BYTELENGTH12 BITS16 BITS20 BITS24 BITSMATCHINGMT2MT1TOLERANCE01975-PrG-033001101010 ERRORS1 ERROR2 ERRORS3 ERRORSC1(1)MT2MT1PL2PL1DB0

Figure 33.

Notes: 1. 2. 3.

Sync byte detect is enabled by programming Bits R4_DB(25:23) to [010] or [011].

This register allows a 28-bit sync byte sequence to be stored internally. If the sync byte detect mode is selected, then the INT/LOCK pin goes high when the sync byte has been detected in Rx mode. Once the sync word detect signal has gone high, it goes low again after nine data bits.

The transmitter must Tx the MSB of the sync byte first and the LSB last to ensure proper alignment in the receiver sync byte detection hardware.

Rev. PrH | Page 32 of 40

Preliminary Technical Data

ADF7020LNA MODEIF FILTERCALMIXERLINEARITYDOTPRODUCTLNACURRENTREGISTER 6—CORRELATOR/DEMODULATOR REGISTER

RxRESETRxDATAINVERTIF FILTER DIVIDERDISCRIMINATOR BWADDRESSBITSDB31DB30DB29DB28DB27DB26DB25DB24DB23DB22DB21DB20DB19DB18DB17DB16DB15DB14TD10DB13DB12DB11DB10DB9DB8DB7DB6DB5DB4DB3DB2DB1C2(1)C4(0)C3(1)C1(0)ML1CA1LG1DP1FC7FC4FC3TD8TD7TD6FC9FC8FC2FC1TD9TD5TD4FC6FC5TD3TD2TD1RI1LI2LI1DB0CA1FILTER CALDP1DOT PRODUCTDEMODRESET0NO CAL0CROSS PRODUCT1CALIBRATE1DOT PRODUCTCDRRESETML1MIXER LINEARITYLG1LNA MODE0DEFAULT0DEFAULTRxDATA1HIGH1REDUCED GAINRI1INVERT0RxDATALI2LI1LNA BIAS1RxDATA00800µA (DEFAULT)FILTER CLOCKFC9.FC6FC5FC4FC3FC2FC1DIVIDE RATIO0.00000110.0000102....................................1.111111511Figure 34.

Notes: 1. See the FSK Correlator/Demodulator section for an example of how to determine register settings. 2. Nonadherence to correlator programming guidelines results in poorer sensitivity.

3. The filter clock is used to calibrate the IF filter. The filter clock divide ratio should be adjusted so that the frequency is 50 kHz. The formula is XTAL/FILTER_CLOCK_DIVIDE.

4. The filter should be calibrated only when the crystal oscillator is settled. The filter calibration is initiated every time Bit R6_DB19 is set high. 5.

Discriminator_BW = (DEMOD_CLK × K)/(800 × 103). See the FSK Correlator/Demodulator section.

Rev. PrH | Page 33 of 40

430-Gr-P57910 ADF7020

Preliminary Technical DataREADBACKSELECTDB8RB3DB7RB2DB6RB1ADCMODEDB5AD2DB4AD1DB3C4(0)CONTROLBITSDB2C3(1)DB1C2(1)DB0C1(1)REGISTER 7—READBACK SETUP REGISTER

RB3READBACK01DISABLEDENABLEDRB2RB1READBACK MODE00110101AFC WORDADC OUTPUTFILTER CALSILICON REVAD2AD1ADC MODE00110101MEASURE RSSIBATTERY VOLTAGETEMP SENSORTO EXTERNAL PIN01975-PrG-035

Figure 35.

Notes: 1. 2. 3. 4.

Readback of the measured RSSI value is valid only in Rx mode. Readback of the battery voltage, the temperature sensor, and the voltage at the external pin is not available in Rx mode, if the ASK demodulator is active or if AGC is enabled.

Readback of the ADC value is valid in Tx mode only if the log amp/RSSI has not been disabled through the power-down bits R8_DB10. The log amp/RSSI section is active per default upon enabling Tx mode.

Readback of the AFC word is valid in Rx mode only if either the linear demodulator or the correlator/demodulator is active. See the Readback Format section for more information.

Rev. PrH | Page 34 of 40

Preliminary Technical Data

ADF7020REGISTER 8—POWER-DOWN TEST REGISTER

INTERNAL Tx/RxSWITCH ENABLEPA ENABLERx MODELNA/MIXERENABLEDEMODENABLEADCENABLEFILTERENABLEVCOENABLESYNTHENABLELOG AMP/RSSICONTROLBITSDB15DB14DB13PD7DB12SW1DB11LR2DB10LR1DB9PD6DB8PD5DB7PD4DB6PD3DB5PD2DB4PD1DB3C4(1)DB2C3(0)DB1C2(0)DB0C1(0)PD901PA (Rx MODE)PA OFFPA ONPD401Tx/Rx SWITCHDEFAULT (ON)OFFLR2XXLR101RSSI MODERSSI OFFRSSI ONPD601DEMOD ENABLEDEMOD OFFDEMOD ONPD501PD401ADC ENABLEADC OFFADC ONPD301PLE1(FROM REG 0)00001PD20011XPD10101XLOOPCONDITIONVCO/PLL OFFPLL ONVCO ONPLL/VCO ONPLL/VCO ONLNA/MIXER ENABLELNA/MIXER OFFLNA/MIXER ONFILTER ENABLEFILTER OFFFILTER ON01975-PrG-036

Figure 36.

Notes: 1. 2.

For a combined LNA/PA matching network, Bit R8_DB12 should always be set to 0. This is the power-up default condition. It is not necessary to write to this register under normal operating conditions.

Rev. PrH | Page 35 of 40

ADF7020

Preliminary Technical DataGAINCONTROLAGCSEARCHREGISTER 9—AGC REGISTER

DIGITALTEST IQFILTERCURRENTFILTERGAINLNAGAINAGC HIGH THRESHOLDAGC LOW THRESHOLDADDRESSBITSDB31DB30DB29DB28DB27DB26DB25DB24DB23DB22DB21DB20DB19DB18DB17DB16DB15DB14DB13DB12DB11DB10DB9DB8DB7DB6DB5DB4DB3DB2DB1C2(0)C4(1)C3(0)C1(1)GC1GH7GH6GH5GH4GH3GH2GH1GS1FG2FG1LG2LG1GL7GL6GL5GL4GL3GL2GL1FI1DB0FI1FILTER CURRENTGS1AGC SEARCHAGC LOW0LOW0AUTO AGCGL7GL6GL5GL4GL3GL2GL1THRESHOLD1HIGH1HOLD SETTING0000001100000102FG2FG1FILTER GAINGC1GAIN CONTROL00000113000010040080AUTO........01241USER........1072........11INVALID111110161111111062111111163RSSI LEVELGH7GH6GH5GH4GH3GH2GH1CODE000000110000010200000113LG2LG1LNA GAIN00001004003........0110........1030........11INVALID100111078100111179101000080Figure 37.

Notes : 1. Default AGC_LOW_THRESHOLD = 27, default AGC_HIGH_THRESHOLD = 76. See the RSSI/AGC Section for more details. 2. AGC high and low settings must be more than 30 apart to ensure correct operation. 3.

LNA gain of 30 is available only if LNA mode, R6_DB15, is set to zero.

Rev. PrH | Page 36 of 40

730-Gr-P57910

Preliminary Technical Data

ADF7020REGISTER 10—AGC 2 REGISTER

RESERVEDUP/DOWNSELECTI/QSELECTI/QI/Q PHASEADJUSTI/Q GAIN ADJUSTAGC DELAYLEAK FACTORPEAK RESPONSEADDRESSBITSDB31DB30DB29SIQ2DB28DB27DB26DB25DB24DB23SIQ1DB22DB21DB20DB19DB18DB17DB16DB15DB14DB13DB12DB11DB10DB9DB8DB7DB6DB5DB4C4 (1)DB3C3 (0)DB2C2 (1)DB1C1 (0)DB001975-PrG-038GC5GC4GC3GC2GC1UD1DH4DH3DH2DH1GL7GL6GL5GL4PH2PH1PR2PH4PH3PR4SIQ2SELECT IQ01PHASE TO I CHANNELPHASE TO Q CHANNELSIQ2SELECT IQ01GAIN TO I CHANNELGAIN TO Q CHANNELDEFAULT = 10DEFAULT = 10DEFAULT = 2PR3PR1R1

Figure 38.

Note: 1.

This register is not used under normal operating conditions.

DB20AFC ENABLEAFC SCALING COEFFICIENTCONTROLBITSDB31DB30DB29DB28DB27DB26DB25DB24DB23DB22DB21DB19DB18DB17DB16DB15DB14DB13DB12DB11DB10DB9DB8DB7DB6DB5DB4DB3DB2DB1C2(1)C4(0)C3(0)01OFFON01975-PrG-039INTERNALAE1AFCC1(0)M16M15M14M13M12M11M10AE1M9M8M7M6M5M4M3M2M1DB0

Figure 39.

Notes: 1. 2.

See the Internal AFC section to program AFC scaling coefficient bits.

The AFC scaling coefficient bits can be programmed using the following formula: AFC_Scaling_Coefficient = Round((500 × 224)/XTAL)

Rev. PrH | Page 37 of 40

ADF7020

Preliminary Technical Data REGISTER 12—TEST REGISTER

DB31PRESCALEROSC TESTANALOG TESTMUXDIGITALTEST MODESCOUNTERRESETSOURCEFORCELD HIGHIMAGE FILTER ADJUSTΣ-∆TEST MODESPLL TEST MODESADDRESSBITSDB30DB29DB28DB27DB26DB25DB24DB23DB22DB21DB20DB19DB18DB17DB16DB15DB14DB13DB12DB11DB10DB9DB8DB7DB6DB5DB4DB3DB2DB1C2(0)C4(1)C3(1)P01PRESCALER4/5 (DEFAULT)8/9CS101CAL SOURCEINTERNALSERIAL IF BW CALDEFAULT = 32. INCREASENUMBER TO INCREASE BWIF USER CAL ONCR1COUNTER RESET01DEFAULTRESET01975-PrG-043C1(0)PREQT1CS1SF6SF5SF4SF3SF2SF1T9T8T7T6T5T4T3T2T1DB0

Figure 40.

Using the Test DAC on the ADF7020 to Implement Analog FM DEMOD and Measuring SNR

The test DAC allows the output of the postdemodulator filter for both the linear and correlator/demodulators (Figure 16 and Figure 17) to be viewed externally. It takes the 16-bit filter output and converts it to a high frequency, single-bit output using a second-order error feedback Σ-∆ converter. The output can be viewed on the XCLKOUT pin. This signal, when IF filtered appropriately, can then be used to •

Monitor the signals at the FSK/ASK postdemodulator filter output. This allows the demodulator output SNR to be measured. Eye diagrams can also be constructed of the received bit stream to measure the received signal quality. Provide analog FM demodulation.

Programming the test register, Register 12, enables the test DAC. Both the linear and correlator/demodulator outputs can be multiplexed into the DAC.

Register 13 allows a fixed offset term to be removed from the signal (to remove the IF component in the ddt case). It also has a signal gain term to allow the usage of the maximum dynamic range of the DAC.

Setting Up the Test DAC

• •

Digital test modes = 7: enables the test DAC, with no offset removal.

Digital test modes = 10: enables the test DAC, with offset removal.

•

While the correlators and filters are clocked by DEMOD_CLK, CDR_CLK clocks the test DAC. Note that, although the test DAC functions in a regular user mode, the best performance is achieved when the CDR_CLK is increased up to or above the frequency of DEMOD_CLK. The CDR block does not function when this condition exists.

The output of the active demodulator drives the DAC, that is, if the FSK correlator/demodulator is selected, the correlator filter output drives the DAC.

Rev. PrH | Page 38 of 40

Preliminary Technical Data

ADF7020REGISTER 13—OFFSET REMOVAL AND SIGNAL GAIN REGISTER

TEST DAC GAINDB31DB30DB29DB28DB27DB26DB25DB24TEST DAC OFFSET REMOVALDB23DB22DB21DB20DB19DB18DB17DB16DB15PULSEEXTENSIONDB14DB13DB12DB11DB10KIDB9DB8DB7DB6KPDB5DB4DB3CONTROLBITSDB2DB1C2(0)DB0C1(1)01975-PrG-044C4(1)PE4000...1PE3000...1PE2001...1PE1010...1PULSE EXTENSIONNORMAL PULSE WIDTH2× PULSE WIDTH3× PULSE WIDTH...16× PULSE WIDTHC3(1)PE4PE3PE2PE1

Figure 41.

Note: 1.

Because the linear demodulator’s output is proportional to frequency, it usually consists of an offset combined with a relatively low signal. The offset can be removed, up to a maximum of 1.0 and gained to use the full dynamic range of the DAC: DAC_input = (2^ Test_DAC_Gain) × (Signal − Test_DAC_Offset_Removal/4096)

Rev. PrH | Page 39 of 40

ADF7020

Preliminary Technical Data0.25 MIN0.25MINPIN 1INDICATOR7.00BSC SQ373648OUTLINE DIMENSIONS

1TOPVIEW0.50BSCBOTTOMVIEW5.254.70 SQ2.250.550.500.45252412135.50BSC1.501.451.400.05 MAX0.02 NOMSEATINGPLANE0.350.200.25COPLANARITY0.05

Figure 42. 48-Lead Micro Lead Frame Chip Scale Package [MLFCSP]

(CP-48M)

7 mm × 7 mm Body

Dimensions shown in millimeters

ORDERING GUIDE

Model

ADF7020BCP

Temperature Range −40°C to +85°C

Package Description

48-Lead Micro Lead Frame Chip Scale Package [MLFCSP]

Package Option CP-48M

Rev. PrH | Page 40 of 40

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