8路抢答器的VHDL语言

1. 设计一个八路智力抢答器，同时供8个选手参赛，编号分别为1到

8。每位选手用一个答题按钮。

2. 给主持人一个控制开关，实现系统的清零和抢答的开始。 3. 具有数据锁存和显示功能。抢答开始后，如果有选手按下了抢答按钮，

其编号立即锁存并显示在LED数码管上，同是扬声器报警。此外，禁止其他选手再次抢答。选手的编号一直保存直到主持人清除。

扩展功能：

1. 具有定时抢答功能，可由主持人设定抢答时间。当抢答开始后。定

时其开始倒计时，并显示在LED上，同时扬声器发声提醒、

2. 选手在规定时间内抢答有效，停止倒计时，并讲倒计时时间显示在

LED上，同时报警

3. 在规定时间内，无人抢答时，电路报警提醒主持人，此后的抢答按

键无效。

4. 选手抢中后，开始答题。规定答题时间为：10s，在规定的时间内，

选手答完题，手动报警。若在规定时间内，未完成答题，报警提示。答题时，显示答题剩余时间。 5. 报警时间定为：100ms

1.

2.系统顶层文件

顶层文件原理图：

VHDL程序：

library IEEE;

use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL;

-- Uncomment the following lines to use the declarations that are -- provided for instantiating Xilinx primitive components. --library UNISIM;

--use UNISIM.VComponents.all;

entity myproject is

port( clk : in std_logic; clear : in std_logic;

--时钟信号

--清零信号

player : in std_logic_vector(7 downto 0); --八个抢答选手输入

settime1 : in std_logic_vector(3 downto 0);--答题时间设置 led_10s : out std_logic_vector(6 downto 0); --10s抢答计时已进行的时间显示 selector : out std_logic_vector(6 downto 0); --抢中选手编码输出 audio : out std_logic; --喇叭响,低有效. endanswer : in std_logic; --答题完成 led_left1 : out std_logic_vector(6 downto 0)

);

end myproject;

architecture Behavioral of myproject is component qiangda port(

set_start : in std_logic;

a : in std_logic_vector(7 downto 0); clk : in std_logic; led : out std_logic_vector(6 downto 0); selector : out std_logic_vector(6 downto 0); selected : out std_logic; alarm : out std_logic );

end component; component dingshiqi port(

selected : in std_logic;

clk : in std_logic;

settime1: in std_logic_vector(3 downto 0); endanswer : in std_logic; alarm : out std_logic;

led : out std_logic_vector(6 downto 0)

);

end component; component baojing port( clk : in std_logic; alarm1 : in std_logic; alarm2 : in std_logic;

alarm3 : in std_logic; audioer : out std_logic

);

end component;

signal selected1 : std_logic; signal start : std_logic:='0'; signal alarm1 : std_logic:='0'; signal alarm2 : std_logic; begin

startall : process(clear) begin if clear'event and clear='1' start<=not start;

end if;

end process;

then

u1: qiangda port map(start,player,clk,led_10s,selector,selected1,alarm1); u2: dingshiqi port map(selected1,clk,settime1,endanswer,alarm2,led_left1); u3: baojing port map(clk,start,alarm1,alarm2,audio); end Behavioral;

系统仿真图：

2、抢答模块VHDL程序：

library IEEE;

use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL;

use IEEE.STD_LOGIC_UNSIGNED.ALL;

-- Uncomment the following lines to use the declarations that are -- provided for instantiating Xilinx primitive components. --library UNISIM;

--use UNISIM.VComponents.all;

entity qiangda is port(

set_start : in std_logic; --开始抢答信号（主持人按）否则一直有效， a : in std_logic_vector(7 downto 0); --八个抢答选手输入 clk : in std_logic; led : out std_logic_vector(6 downto 0); --10s抢答计时已进行的时间显示 selector : out std_logic_vector(6 downto 0); --抢中选手编码输出 selected : out std_logic; alarm : out std_logic); end qiangda;

architecture Behavioral of qiangda is

signal deny1 : std_logic:='0'; --作为选中后标志 signal deny2 : std_logic:='0'; --作为抢答计时结束标志 signal timeon : integer range 0 to 15 :=0; signal cnt1 : integer range 0 to 32000000; begin

alarm<=deny1 or deny2; selected<=deny1;

select1 : process(set_start,deny2,a) begin if set_start='0' then deny1<='0'; selector<=\"0110000\"; elsif(deny1='0' and deny2='0' ) then case a is when \"10000000\"=> selector<=\"1001111\"; deny1<='1'; when \"01000000\"=> selector<=\"0010010\"; deny1<='1'; when \"00100000\"=> selector<=\"0000110\"; deny1<='1'; when \"00010000\"=> selector<=\"1001100\"; deny1<='1'; when \"00001000\"=> selector<=\"0100100\"; deny1<='1'; when \"00000100\"=> selector<=\"0100000\"; deny1<='1'; when \"00000010\"=> selector<=\"0001111\"; deny1<='1'; when \"00000001\"=> selector<=\"0000000\"; deny1<='1'; when others => selector<=\"1111111\"; --all unlaw states!!! end case; end if; end process;

time10s : process(clk,deny1,set_start) begin if (clk'event and clk='1') then if set_start='0' then deny2<='0'; timeon<=10; cnt1<=0; elsif deny1='1' then timeon<=timeon; elsif timeon/=0 then if cnt1/=32000000 then cnt1<=cnt1+1; else timeon<=timeon-1; cnt1<=0; end if; else

deny2<='1'; end if; end if; end process;

ledshow : process(timeon) begin

case timeon is when 0=> led<=\"0000001\"; --0 when 1=> led<=\"1001111\"; --1 when 2=> led<=\"0010010\"; --2 when 3=> led<=\"0000110\"; --3 when 4=> led<=\"1001100\"; --4 when 5=> led<=\"0100100\"; --5 when 6=> led<=\"0100000\"; --6 when 7=> led<=\"0001111\"; --7 when 8=> led<=\"0000000\"; --8 when 9=> led<=\"0000100\"; --9 when others => led<=\"1111111\"; --未选中的状态,不显示 end case; end process; end Behavioral;

抢答电路仿真图：

3.答题模块VHDL程序：（定时）

library IEEE;

use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL;

use IEEE.STD_LOGIC_UNSIGNED.ALL;

-- Uncomment the following lines to use the declarations that are -- provided for instantiating Xilinx primitive components. --library UNISIM;

--use UNISIM.VComponents.all;

entity dingshiqi is

--设置答题时间,并计数,显示剩余时间,并将计数剩余时间转换为LED码输出。 port ( selected : in std_logic; clk : in std_logic;

settime1 : in std_logic_vector(3 downto 0); endanswer : in std_logic; alarm : out std_logic; led : out std_logic_vector(6 downto 0)); end dingshiqi;

architecture Behavioral of dingshiqi is signal cnt1 : integer range 0 to 32000000; signal time1 : std_logic:='0'; signal alarm1 : std_logic:='0'; signal alarm2 : std_logic:='0'; signal num1 : integer range 0 to 15; begin

time1s : process(clk,selected) ---- 一秒定时 begin if selected='1' then if (clk'event and clk='1') then if cnt1=32000000 then time1<=not time1; cnt1<=0; else cnt1<=cnt1+1; end if; end if; end if; end process;

settimeNs : process(time1,selected,alarm2) begin if selected='0' then alarm1<='0'; num1<=conv_integer(settime1); else if alarm2/='1' then if (time1'event and time1='1') then if num1/=0 then num1<=num1-1; alarm1<='0'; else alarm1<='1'; end if; end if;

else num1<=num1; end if; end if;

end process;

alarmer :process(endanswer,selected) --答题完成 begin if selected='1' then

if endanswer='1' then alarm2<='1'; end if; else alarm2<='0'; end if; end process;

alarm<=alarm1 or alarm2; led_show1 : process(num1) begin case num1 is when 0=> led<=\"0000001\"; --0 when 1=> led<=\"1001111\"; --1 when 2=> led<=\"0010010\"; --2 when 3=> led<=\"0000110\"; --3 when 4=> led<=\"1001100\"; --4 when 5=> led<=\"0100100\"; --5 when 6=> led<=\"0100000\"; --6 when 7=> led<=\"0001111\"; --7 when 8=> led<=\"0000000\"; --8 when 9=> led<=\"0000100\"; --9 when others => led<=\"1111111\"; --未选中的状态,不显示 end case; end process; end Behavioral;

选手抢答模块设计 4.2.2 锁存模块设计 4.2.3计时模块设计 4.2.4声音报警模块设计 4.2.4声音信号产生模块

系统顶层文件 2、抢答模块VHDL程序： 3. 答题模块VHDL程序：（定时） 4.3顶层文件设计