The MC74VHCT573A is an advanced high speed CMOS octal latchwith 3−state output fabricated with silicon gate CMOS technology. Itachieves high speed operation similar to equivalent Bipolar SchottkyTTL while maintaining CMOS low power dissipation.
This 8−bit D−type latch is controlled by a latch enable input and anoutput enable input. When the output enable input is high, the eightoutputs are in a high impedance state.
The VHCT inputs are compatible with TTL levels. This device canbe used as a level converter for interfacing 3.3 V to 5.0 V, because ithas full 5.0 V CMOS level output swings.
The VHCT573A input and output (when disabled) structuresprovide protection when voltages between 0 V and 5.5 V are applied,regardless of the supply voltage. These input and output structureshelp prevent device destruction caused by supplyvoltage−input/output voltage mismatch, battery backup, hot insertion,etc.
Features
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MARKINGDIAGRAMS
20VHCT573AAWLYYWWG1
1SOIC−20WBSUFFIX DWCASE 751D
••••••••••••
20
VHCT573AALYWGG1
High Speed: tPD = 7.7 ns (Typ) at VCC = 5.0 V
Low Power Dissipation: ICC = 4 mA (Max) at TA = 25°CTTL−Compatible Inputs: VIL = 0.8 V; VIH = 2.0 V
Power Down Protection Provided on Inputs and OutputsBalanced Propagation Delays
Designed for 4.5 V to 5.5 V Operating RangeLow Noise: VOLP = 1.6 V (Max)
Pin and Function Compatible with Other Standard Logic FamiliesLatchup Performance Exceeds 300 mAESD Performance:
Human Body Model > 2000 V;Machine Model > 200 V
Chip Complexity: 234 FETs or 58.5 Equivalent GatesThese Devices are Pb−Free and are RoHS Compliant
1TSSOP−20SUFFIX DTCASE 948E
A=Assembly LocationWL, L=Wafer LotYY, Y=Year
WW, W=Work WeekG or G= Pb−Free Package
(Note: Microdot may be in either location)
FUNCTION TABLE
INPUTSOELLLHLEHHLXDHLXXOUTPUTQHLNo ChangeZORDERING INFORMATION
See detailed ordering and shipping information in the packagedimensions section on page 4 of this data sheet.
© Semiconductor Components Industries, LLC, 2011
June, 2011 − Rev. 5
1
Publication Order Number:
MC74VHCT573A/D
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MC74VHCT573A
D0D1D2
DATAINPUTS
D3D4D5D6D7LEOE234567891111918171615141312Q0Q1Q2Q3Q4Q5Q6Q7NONINVERTINGOUTPUTS
OED0D1D2D3D4D5D6D7GND
1234567891020191817161514131211VCCQ0Q1Q2Q3Q4Q5Q6Q7LE
Figure 1. Logic Diagram
Figure 2. Pin Assignment
MAXIMUM RATINGS
SymbolVCCVinVoutIIK
DC Supply VoltageDC Input VoltageDC Output VoltageInput Diode Current
ParameterValue– 0.5 to + 7.0– 0.5 to + 7.0
Outputs in 3−StateHigh or Low State
– 0.5 to + 7.0– 0.5 to VCC + 0.5
− 20±20±25±75500450
UnitVVVmAmAmAmA
IOKIoutPD
Output Diode Current (VOUT < GND; VOUT > VCC)DC Output Current, per Pin
DC Supply Current, VCC and GND PinsPower Dissipation in Still Air,Storage Temperature
ICC
SOIC Package†
TSSOP Package†
mW_C
This device contains protectioncircuitry to guard against damagedue to high static voltages or electricfields. However, precautions mustbe taken to avoid applications of anyvoltage higher than maximum ratedvoltages to this high−impedance cir-cuit. For proper operation, Vin andVout should be constrained to therange GND v (Vin or Vout) v VCC.Unused inputs must always betied to an appropriate logic voltagelevel (e.g., either GND or VCC).Unused outputs must be left open.
Tstg
– 65 to + 150
Maximum ratings are those values beyond which device damage can occur. Maximum ratings
applied to the device are individual stress limit values (not normal operating conditions) and arenot valid simultaneously. If these limits are exceeded, device functional operation is not implied,damage may occur and reliability may be affected.
†Derating−SOIC Packages: – 7 mW/_C from 65_ to 125_C
TSSOP Package: − 6.1 mW/_C from 65_ to 125_C
RECOMMENDED OPERATING CONDITIONS
SymbolVCCVinVoutTA
ParameterMin4.500
0
Max5.55.5
UnitVVV
DC Supply VoltageDC Input Voltage
DC Output Voltage
Outputs in 3−State
High or Low State
5.5VCC
Operating Temperature− 400
+ 8520
_C
tr, tfInput Rise and Fall TimeVCC =5.0V ±0.5V
ns/V
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MC74VHCT573A
DC ELECTRICAL CHARACTERISTICS
SymbolVIHVILVOHVOLIinIOZICC
Parameter
Test Conditions
VCC
V
TA = 25°CTyp
TA = − 40 to 85°CMin2.0
Max0.8
4.43.80
Min2.0
Max0.8
UnitVVV
Minimum High−Level Input VoltageMaximum Low−Level Input VoltageMinimum High−Level Output
VoltageVin = VIH or VIL
IOH = − 50mAIOH = − 8mAIOL = 50mAIOL = 8mAVin = 5.5 V or GNDVin = VIL or VIH
Vout = VCC or GNDVin = VCC or GND
4.5 to 5.54.5 to 5.54.54.54.54.50 to 5.55.55.55.50
4.43.94
4.5
Maximum Low−Level Output
VoltageVin = VIH or VIL
0.00.10.36±0.1± 0.254.0
0.10.44±1.0± 2.540.01.505.0
V
Maximum Input Leakage CurrentMaximum 3−State Leakage CurrentMaximum Quiescent Supply CurrentQuiescent Supply CurrentOutput Leakage Current
mAmAmA
ICCT
Per Input: VIN = 3.4V
Other Input: VCC or GNDVOUT = 5.5V
1.350.5
mAmA
IOPD
AC ELECTRICAL CHARACTERISTICS (Input tr = tf = 3.0ns)
TA = 25°CTyp7.7
8.55.15.96.37.18.8
TA = − 40 to 85°CMin1.01.01.01.01.01.01.0
Max13.514.5
SymboltPLH,
tPHLtPLH,tPHLtPZL,tPZHtPLZ,tPHZ
ParameterTest ConditionsMinMaxUnitnsnsnsnsnspFpF
Maximum Propagation Delay,
LE to Q
Maximum Propagation Delay, D to Q
Output Enable Time, OE to QVCC = 5.0 ± 0.5VVCC = 5.0 ± 0.5V
CL = 15pFCL = 50pFCL = 15pFCL = 50pFCL = 15pFCL = 50pFCL = 50pFCL = 50pF
12.313.38.59.5
9.5
10.5
VCC = 5.0 ± 0.5V
RL = 1kWVCC = 5.0 ± 0.5VRL = 1kWVCC = 5.5 ± 0.5V(Note 1)
10.911.911.21.0
12.513.512.01.010
Output Disable Time,
OE to QtOSLH,
tOSHLCin
Output to Output SkewMaximum Input Capacitance
46
10
Cout
Maximum 3−State Output Capacitance
(Output in High−Impedance State)
Typical @ 25°C, VCC = 5.0V
CPD
Power Dissipation Capacitance (Note 2)
25
pF
1.Parameter guaranteed by design. tOSLH = |tPLHm − tPLHn|, tOSHL = |tPHLm − tPHLn|.
2.CPD is defined as the value of the internal equivalent capacitance which is calculated from the operating current consumption without load.Average operating current can be obtained by the equation: ICC(OPR) = CPD VCC fin + ICC/8 (per latch). CPD is used to determine theno−load dynamic power consumption; PD = CPD VCC2 fin + ICC VCC.
NOISE CHARACTERISTICS (Input tr = tf = 3.0ns, CL = 50 pF, VCC = 5.0V)
TA = 25°C
SymbolVOLPVOLVVIHDVILD
Quiet Output Maximum Dynamic VOLQuiet Output Minimum Dynamic VOLMinimum High Level Dynamic Input VoltageMaximum Low Level Dynamic Input Voltage
Parameter
Typ1.2−1.2
Max1.6−1.62.00.8
UnitVVVV
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MC74VHCT573A
TIMING REQUIREMENTS (Input tr = tf = 3.0ns)
TA = 25°C
Symboltw(h)tsuth
Parameter
Minimum Pulse Width, LEMinimum Setup Time, D to LEMinimum Hold Time, D to LE
Test ConditionsVCC = 5.0 ±0.5VVCC = 5.0 ± 0.5VVCC = 5.0 ± 0.5V
Typ
Limit6.51.53.5
TA = − 40 to 85°C
Limit8.51.53.5
Unitnsnsns
ORDERING INFORMATION
Device
MC74VHCT573ADWGMC74VHCT573ADWRGMC74VHCT573ADTGMC74VHCT573ADTRG
PackageSOIC−20WB(Pb−Free)SOIC−20WB(Pb−Free)TSSOP−20*TSSOP−20*
Shipping†38 Units / Rail1000 / Tape & Reel75 Units / Rail2500 / Tape & Reel
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel PackagingSpecifications Brochure, BRD8011/D.*This package is inherently Pb−Free.
tw3V
D
tPLHQ
1.5V1.5VtPHLGNDVOHVOL
Q
1.5VLE
1.5V3VGND
tPLHtPHLVOHVOL
Figure 3. Switching WaveformFigure 4. Switching Waveform
3V
OE1.5VtPZLQ
1.5VtPZHQ
1.5VtPHZtPLZGNDHIGH
IMPEDANCE
VOL +0.3VVOH -0.3VHIGH
IMPEDANCE
LE
1.5VGND
D
1.5VtsuthGND3V
VALID3V
Figure 5. Switching WaveformFigure 6. Switching Waveform
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MC74VHCT573A
TEST POINTOUTPUTDEVICEUNDERTESTCL*
DEVICEUNDERTESTTEST POINTOUTPUT1 kWCONNECT TO VCC WHENTESTING tPLZ AND tPZL.CONNECT TO GND WHENTESTING tPHZ AND tPZH.
CL**Includes all probe and jig capacitance
*Includes all probe and jig capacitance
Figure 7. Test CircuitFigure 8. Test Circuit
D0
2DLEQ19Q0
D1
3DLEQ18Q1
D2
4DLEQ17Q2
D3
5DLEQ16Q3
D4
6DLEQ15Q4
D5
7DLEQ14Q5
D6
8DLEQ13Q6
D7
9DLEQ12Q7
LE11OE1Figure 9. Expanded Logic Diagram
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MC74VHCT573A
PACKAGE DIMENSIONS
TSSOP−20CASE 948E−02ISSUE C
20X REFK0.15 (0.006)TUS0.10 (0.004)MTUSVSKK12XL/22011JJ1B−U−NLSECTION N−N0.25 (0.010)MPIN 1IDENT1100.15 (0.006)TUSA−V−NFDETAIL E
CD0.100 (0.004)−T−SEATINGPLANEGHDETAIL ENOTES:
1.DIMENSIONING AND TOLERANCING PERANSI Y14.5M, 1982.
2.CONTROLLING DIMENSION:MILLIMETER.
3.DIMENSION A DOES NOT INCLUDEMOLD FLASH, PROTRUSIONS OR GATEBURRS. MOLD FLASH OR GATE BURRSSHALL NOT EXCEED 0.15 (0.006) PER SIDE.4.DIMENSION B DOES NOT INCLUDEINTERLEAD FLASH OR PROTRUSION.INTERLEAD FLASH OR PROTRUSION
SHALL NOT EXCEED 0.25 (0.010) PER SIDE.5.DIMENSION K DOES NOT INCLUDEDAMBAR PROTRUSION. ALLOWABLEDAMBAR PROTRUSION SHALL BE 0.08(0.003) TOTAL IN EXCESS OF THE KDIMENSION AT MAXIMUM MATERIALCONDITION.
6.TERMINAL NUMBERS ARE SHOWN FORREFERENCE ONLY.
7.DIMENSION A AND B ARE TO BEDETERMINED AT DATUM PLANE −W−.
MILLIMETERSINCHESDIMMINMAXMINMAXA6.406.600.2520.260B4.304.500.1690.177C1.200.047------D0.050.150.0020.006F0.500.750.0200.030G0.65 BSC0.026 BSC−W−H0.270.370.0110.015J0.090.200.0040.008J10.090.160.0040.006K0.190.300.0070.012K10.190.250.0070.010L6.40 BSC0.252 BSCM0 8 0 8 ____SOLDERING FOOTPRINT
7.0610.65PITCH
0.36
16X
16X1.26DIMENSIONS: MILLIMETERShttp://onsemi.com
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MC74VHCT573A
PACKAGE DIMENSIONS
SOIC−20 WBDW SUFFIXCASE 751D−05ISSUE G
DA11X 45_qHMBM2010X0.25ENOTES:
1.DIMENSIONS ARE IN MILLIMETERS.
2.INTERPRET DIMENSIONS AND TOLERANCESPER ASME Y14.5M, 1994.
3.DIMENSIONS D AND E DO NOT INCLUDE MOLDPROTRUSION.
4.MAXIMUM MOLD PROTRUSION 0.15 PER SIDE.5.DIMENSION B DOES NOT INCLUDE DAMBARPROTRUSION. ALLOWABLE PROTRUSIONSHALL BE 0.13 TOTAL IN EXCESS OF BDIMENSION AT MAXIMUM MATERIALCONDITION.
DIMAA1BCDEeHhLqMILLIMETERSMINMAX2.352.650.100.250.350.490.230.3212.6512.957.407.601.27 BSC10.0510.550.250.750.500.900 7 __11020XB0.25
MBTA
SB
SAeSEATINGPLANEh18XA1TCON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further noticeto any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liabilityarising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.“Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. Alloperating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rightsnor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applicationsintended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. ShouldBuyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates,and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or deathassociated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an EqualOpportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.
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