用VHDL编程实现一个器件的功能！！！急急急

发布网友 发布时间：2022-04-22 00:05

我来回答

共3个回答

热心网友 时间：2023-07-20 03:49

VHDL语言设计四位全加器：
library IEEE;
use IEEE.Std_logic_11.ALL;
entity pro1 is
port(A1,B1,G1BAR,A0,B0,G0BAR:in std_logic;
Y20,Y21,Y22,Y23,Y10,Y11,Y12,Y13:out std_logic);
end pro1;

architecture pro1_arch of pro1 is
begin
Y10<='0' when(B0='0') and ((A0='0') and (G0BAR='0')) else '1';
Y11<='0' when(B0='0') and ((A0='1') and (G0BAR='0')) else '1';
Y12<='0' when(B0='1') and ((A0='0') and (G0BAR='0')) else '1';
Y13<='0' when(B0='1') and ((A0='1') and (G0BAR='0')) else '1';
Y20<='0' when(B1='0') and ((A1='0') and (G1BAR='0')) else '1';
Y21<='0' when(B1='0') and ((A1='1') and (G1BAR='0')) else '1';
Y22<='0' when(B1='1') and ((A1='0') and (G1BAR='0')) else '1';
Y23<='0' when(B1='1') and ((A1='1') and (G1BAR='0')) else '1';
end pro1_arch;

能实现四位二进制数全加的数字电路模块，称之为四位全加器。
http://ke.baidu.com/link?url=GaCnz6D-_GQfu1rs_YfE_cZKiwRMcRtEpeLDS2Nn-0UlA39xIq_E2Vw8ttNptjB-kaKIblYblcLCXucw3cbaIK

热心网友 时间：2023-07-20 03:49

设计一个四位的全加器(功能说明见实验二.(二).2) 6.设计一个7位奇偶校验电路(功能说明见实验二.(二).4) 7.数字比较器,设计4位二进制数字比较器 (二)基于VHDL的时序电路设计 用VHDL语言编写实现下列器件功能的程序并进行编译,...

热心网友 时间：2023-07-20 03:49

library IEEE;
use IEEE.Std_logic_11.ALL;
entity pro1 is
port(A1,B1,G1BAR,A0,B0,G0BAR:in std_logic;
Y20,Y21,Y22,Y23,Y10,Y11,Y12,Y13:out std_logic);
end pro1;

architecture pro1_arch of pro1 is
begin
Y10<='0' when(B0='0') and ((A0='0') and (G0BAR='0')) else '1';
Y11<='0' when(B0='0') and ((A0='1') and (G0BAR='0')) else '1';
Y12<='0' when(B0='1') and ((A0='0') and (G0BAR='0')) else '1';
Y13<='0' when(B0='1') and ((A0='1') and (G0BAR='0')) else '1';
Y20<='0' when(B1='0') and ((A1='0') and (G1BAR='0')) else '1';
Y21<='0' when(B1='0') and ((A1='1') and (G1BAR='0')) else '1';
Y22<='0' when(B1='1') and ((A1='0') and (G1BAR='0')) else '1';
Y23<='0' when(B1='1') and ((A1='1') and (G1BAR='0')) else '1';
end pro1_arch;